Intel® Stratix® 10 Configuration User Guide

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ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins

Set a false path for PFL II IP input pins

You can set the pfl_nreset input reset pin to a false path since this pin is asynchronous.

set_false_path -from [get_ports {pfl_nreset}] -to *

Set input delay to PFL II IP input pins

Example below sets the input delay for the pfl_flash_access_granted pin.
  • You don't have to constraint the path when you use the device arbiter logic to control the pin,
  • You don't have to constraint the path when not using the device arbiter logic or the external processor to control the pin and you loopback the pfl_flash_access_request signal to the pfl_flash_access_granted pin.
  • You can constraint the path when a processor or an external device controls the pfl_flash_access_granted pin.
set_input_delay -clock {clk_50m_sysmax} -max [<pfl_flash_access_granted_tco_max> + <pfl_flash_access_granted_tracemax>] [get_ports {pfl_flash_access_granted}]
set_input_delay -clock {clk_50m_sysmax} -min [<pfl_flash_access_granted_tco_min> + <pfl_flash_access_granted_tracemin>] [get_ports {pfl_flash_access_granted}]

Set a false path for fpga_pgm[] input pin

You can set a false path to quasi-static signals such as reset and configuration signals (fpga_conf_done, fpga_nstatus) that are stable for a long periods of time.

set_false_path -from [get_ports {fpga_pgm[]}] -to * 

Set input delay to pfl_nreconfigure input pin

If you use the external component to drive this pin, you must set the input delay path to drive the pfl_nreconfigure pin.

set_input_delay -clock {clk_50m_sysmax} -max [<pfl_nreconfigure_tco_max> + <pfl_nreconfigure_tracemax>] \
[get_ports {pfl_nreconfigure}]

set_input_delay -clock {clk_50m_sysmax} -min [<pfl_nreconfigure_tco_min> + <pfl_nreconfigure_tracemin>] \
[get_ports {pfl_nreconfigure}]

Set input delay to pfl_reset_watchdog pin

If you use the external component to drive this pin, you must set the input delay path to drive the pfl_reset_watchdog pin.
set_input_delay -clock {clk_50m_sysmax} -max [$pfl_reset_watchdog_tco_max + $pfl_reset_watchdog_tracemax] \
[get_ports {pfl_nreconfigure}]

set_input_delay -clock {clk_50m_sysmax} -min [$pfl_reset_watchdog_tco_min + $pfl_reset_watchdog_tracemin] \
[get_ports {pfl_nreconfigure}]

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