Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1.7.3.2. Mapping PFL II IP Core and Flash Address

The address connections between the PFL II IP core and the flash memory device vary depending on the flash memory device vendor and data bus width.
Figure 28.  Flash Memory in 8-Bit ModeThe address connection between the PFL II IP core and the flash memory device are the same.
Figure 29.  Flash Memories in 16-Bit ModeThe flash memory addresses in 16-bit flash memory shift one bit down in comparison with the flash addresses in PFL II IP core. The flash address in the flash memory starts from bit 1 instead of bit 0.
Figure 30. Cypress and Micron M28, M29 Flash Memory in 8-Bit ModeThe flash memory addresses in Cypress 8-bit flash shifts one bit up. Address bit 0 of the PFL II IP core connects to data pin D15 of the flash memory.
Figure 31. Cypress and Micron M28, M29 Flash Memory in 16-Bit ModeThe address bit numbers in the PFL II IP core and the flash memory device are the same.

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