The Intel® Stratix® 10 device has specific clock requirements for PCIe* , HPS EMIF, eSRAM, and the High Bandwidth Memory (HBM2) IP. These clock requirements must be met before the FPGA configuration begins.
To avoid configuration failures, the Intel® Stratix® 10
device requires clocks for the PCIe*
, HPS EMIF, eSRAM, the HBM2 IP, and all E-tile transceiver reference clocks. You must provide a free-running, stable reference clock to these blocks before configuration begins and throughout the entire user mode. The clock frequencies must match the frequency settings specified in the Intel® Quartus® Prime
software during configuration. Stopping the reference clock during the user mode may result in a functional failure. This reference clock is in addition to the configuration clock requirements for an internal or external oscillator described in OSC_CLK_1 Requirements
. These blocks and their specific clock names are as listed below.
- HBM2: pll_ref_clk and ext_core_clk
- eSRAM: CLK_ESRAM_[0,1]p and CLK_ESRAM_[0,1]n
- HPS: HPS_OSC_CLK, when HPS enabled 3
- HPS EMIF: pll_ref_clk
- L- and H-tile PCIe* channels: REFCLK_GXB
- E-tile: REFCLK_GXE
In the Intel® Stratix® 10 TX/MX devices, when using PRESERVE_UNUSED_XCVR_CHANNEL_QSF assignment to protect unused channels by enabling transceiver circuits, you must provide a free-running and stable reference clock to the transceiver circuit.
Note: The transceiver power supplies must be at nominal levels for successful configuration. You can use the VCC and VCCP power supplies for limited transceiver channel testing. Designs that include many transceivers require an auxiliary power supply to operate reliably.
Intel® Quartus® Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option, select HPS First in the dialog box.
HPS First Configuration
Intel® Stratix® 10
devices have the option of booting the HPS before configuring the FPGA core logic. This method is known as the HPS first configuration. When you choose this option in the Intel® Quartus® Prime Pro Edition
software, the following clocks must be operational prior to the FPGA I/O, HPS I/O, and HPS boot, also called a phase 1 configuration:
- HPS reference clock: HPS_OSC_CLK
- HPS EMIF (when in use): pll_ref_clk
- E-tile transceivers: REFCLK_GXE
The remaining clocks specified in the FPGA Configuration must be fully operational prior the FPGA core logic configuration, also called phase 2 configuration. For more information on HPS boot first mode, refer to the Intel® Stratix® 10 SoC FPGA Boot User Guide.
If you use the FPGA to HPS free clock as the HPS PLL reference clock, the HPS_OSC_CLK
clock may not be required.