Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Document Table of Contents PFL II IP Recommended Design Constraints for using CFI Flash

Create a FLASH_CLK clock

Example below assigns CFI flash clock pin (flash_clk) to the flash clock. You constrain the flash_clk pin only when using burst mode.

create_generated_clock -name FLASH_CLK -source [get_ports {clk_50m_max5}] [get_ports {flash_clk}]

Set output delay for output pins

Example below sets the output delay for CFI flash output pins.

set flash_data_tracemax 0.250
set flash_data_tracemin 0.000
set flash_clk_tracemax 0.250
set flash_clk_tracemin 0.000
set flash_Tsu 3.500
set flash_Th 2.000
set flash_out_max_dly [expr $flash_data_tracemax + $flash_Tsu - $flash_clk_tracemin]
set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax]

#Note: For normal mode, the clock is referred to input pfl_clk clock(clk_50m_max5) of PFL II IP. 
#If burst mode is used, the clock is referred to flash clock of PFL II IP.   

set_output_delay -add_delay -max -clock [get_clocks {clk_50m_max5}] \
$flash_out_max_dly [get_ports {flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}]

set_output_delay -add_delay -min -clock [get_clocks {clk_50m_max5}] \
$flash_out_min_dly [get_ports { flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}]

#Only need to constraint flash_advn pin when using burst mode.
set_output_delay -add_delay -max -clock [get_clocks { FLASH_CLK }] $flash_out_max_dly [get_ports {flash_nadv}]
set_output_delay -add_delay -min -clock [get_clocks { FLASH_CLK }] $flash_out_min_dly [get_ports {flash_nadv}]

Set input delay for input pins

Example below sets the input delay for CFI flash data.

# For Normal Mode
set flash_noe_tracemax 0.250
set flash_noe_tracemin 0.000
set flash_tco_max 7.000
set flash_tco_min 0.000
set normal_in_max_dly [expr $flash_data_tracemax + $flash_tco_max + $ flash_noe_tracemax]
set normal_in_min_dly [expr $flash_data_tracemin + $flash_tco_min + $ flash_noe_tracemin]

set_input_delay -clock { clk_50m_max5 } -max $normal_in_max_dly [get_ports {flash_data[*]}]
set_input_delay -clock { clk_50m_max5 } -min $normal_in_min_dly [get_ports {flash_data[*]}]
# For Burst mode
set flash_tco_max 5.500
set flash_tco_min 2.000
set burst_in_max_dly [expr $flash_data_tracemax + $flash_tco_max + $flash_clk_tracemax]
set burst_in_min_dly [expr $flash_data_tracemin + $flash_tco_min + $flash_clk_tracemin]

set_input_delay -clock { FLASH_CLK } -max $burst_in_max_dly [get_ports {flash_data[*]}]
set_input_delay -clock { FLASH_CLK } -min $burst_in_min_dly [get_ports {flash_data[*]}]

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