Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.2.4. AS Configuration Timing Parameters

Figure 40. AS Configuration Serial Output Timing Diagram
Figure 41. AS Configuration Serial Input Timing Diagram
Table 32.  Text_delay as a Function of AS_CLK Frequency
Symbol Configuration Clock Source Frequency Min (ns) Max (ns)
Text_delay Internal Oscillator 115 MHz 0 20
77 MHz 0 20
58 MHz 0 20
25 MHz 0 24
OSC_CLK_1 125 Mhz 0 18
100 MHz 0 24
71.5 MHz 0 35
50 MHz 0 24
25 MHz 0 24
Note: For more information about the timing parameters, refer to the Intel® Stratix® 10 Device Datasheet.

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