Intel® Stratix® 10 Configuration User Guide

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ID 683762
Date 5/30/2022
Public
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2.1. Intel® Stratix® 10 Configuration Timing Diagram

Figure 4. Power-On, Configuration, and Reconfiguration Timing Diagram

The SDM drives Intel® Stratix® 10 device configuration.

Power-On Status

The power-on reset (POR) holds the Intel® Stratix® 10 device in the reset state until the power supply outputs are within the recommended operating range. tRAMP defines the maximum power supply ramp time. If power supplies ramp time do not meet the tRAMP time, the Intel® Stratix® 10 device I/O pins state is unknown.

For more information about POR refer to the Intel® Stratix® 10 Power Management User Guide. For more information about tRAMP refer to the Intel® Stratix® 10 Device Datasheet.

Initial Configuration Timing

The first section of the figure shows the expected timing for initial configuration after a normal power-on reset . Initially, the application logic drives the nCONFIG signal low (POR). Under normal conditions nSTATUS follows nCONFIG because nSTATUS reflects the current configuration state. nCONFIG must only change when it has the same value as nSTATUS.

When an error occurs, nSTATUS pulses low and asserts high when the device is ready to accept reconfiguration.

The numbers in the Initial Configuration part of the timing diagram mark the following events:

  1. The SDM boots up and samples the MSEL signals to determine the specified FPGA configuration scheme. The SDM does not sample the MSEL pins again until the next power cycle.
  2. With the nCONFIG signal low, the SDM enters Idle mode after booting. Holding nCONFIG signal low during power up is optional.
  3. When the external host drives nCONFIG signal high, the SDM initiates configuration. The SDM drives the nSTATUS signal high, signaling the beginning of FPGA configuration. The SDM receives the configuration bitstream on the interface that the MSEL bus specified in Step 1. Throughout the configuration, it is possible for AVST_READY to deassert which would require AVST_VALID to deassert within six cycles.
  4. The SDM drives the CONF_DONE signal high, indicating the SDM received the bitstream successfully.
  5. When the Intel® Stratix® 10 device asserts INIT_DONE to indicate the FPGA has entered user mode. GPIO pins exit the high impedance state. The time between the assertion of CONF_DONE and INIT_DONE is variable.

    For FPGA first configuration, INIT_DONE asserts after initialization of the FPGA fabric, including registers and state machines.

    For HPS first configuration, the HPS application controls the time between CONF_DONE and INIT_DONE. INIT_DONE does not assert until after the software running on the HPS such as U-Boot or the operating system (OS) initiates the configuration, the FPGA configures and enters user mode.

    The entire device does not enter user mode simultaneously. Intel requires you to include reset release as described in the Including the Reset Release Intel FPGA IP in Your Design. Use the nINIT_DONE output of the Reset Release Intel® FPGA IP to hold your application logic in the reset state until the entire FPGA fabric is in user mode. Failure to include this IP in your design may result in intermittent application logic failures.

Reconfiguration Timing

The second event in the timing diagram illustrates the Intel® Stratix® 10 device reconfiguration. If you change the MSEL setting after power-on, you must power-cycle the Intel® Stratix® 10. Power cycling forces the SDM to sample the MSEL pins before reconfiguring the device.

The numbers in the Reconfiguration part of the timing diagram mark the following events:

  1. The external host drives nCONFIG signal low. nCONFIG signal must be held low until the device drives the nSTATUS signal low.
  2. The SDM initiates device cleaning.
  3. The SDM drives the nSTATUS signal low when device cleaning is complete.
  4. The external host drives the nCONFIG signal high to initiate reconfiguration.
  5. The SDM drives the nSTATUS signal high signaling the device is ready for reconfiguration and starts to reconfigure.
    Note: If you do not monitor the nSTATUS signal, pulse the nCONFIG signal low for at least 1000 ms to initiate a reconfiguration request.

Recoverable Configuration Error

Figure 5. Recoverable Error during Reconfiguration Timing Diagram

The numbers in the Configuration Error part of the timing diagram mark the following events:

  1. The SDM drives nSTATUS signal low for a period of time specified in the Intel® Stratix® 10 Device Datasheet to indicate a recoverable configuration error. The Intel® Stratix® 10 device may not assert CONF_DONE indicating that device did not receive the complete configuration bitstream. The device does not assert INIT_DONE indicating that the configuration did not complete successfully. nCONFIG should continue to be driven high until after nSTATUS has returned back to high state.

    If an error occurs during JTAG configuration, the SDM does not change the state of the nSTATUS signal. You can monitor the error messages that the Intel® Quartus® Prime Pro Edition Programmer generates for error reporting.

  2. The SDM enters the error state.
  3. The SDM enters the idle state if the nCONFIG signal drives to low. The device is ready for reconfiguration by driving a low to high transition on nCONFIG. You can also power cycle the device by following the device power down sequence.
    Note: The nCONFIG signal can only change levels when it has the same value as nSTATUS. This restriction means that when nSTATUS = 1, nCONFIG can transition from 1 to 0. When nSTATUS = 0, nCONFIG can transition from 0 to 1. Apart from error reporting, nSTATUS only changes to follow nCONFIG.

Unrecoverable Configuration Error

Figure 6. Unrecoverable Error during Reconfiguration Timing Diagram

In rare instances, a configuration error or a security event may be unrecoverable. In these cases, the SDM drives nSTATUS low and it stays low. You must perform a power cycle to restart the reconfiguration process. To ensure error recovery under all reconfiguration circumstances, Intel recommends that you design your system to continuously monitor nSTATUS and enable device power cycling if needed.

Note that in the case of an anti-tamper event or a double bit ECC error in the SDM RAM, nSTATUS is also asserted low and stays low.

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