Intel® Stratix® 10 Configuration User Guide

Download
ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1. Avalon-ST Configuration

The Avalon® -ST configuration scheme replaces the FPP mode available in earlier device families. Avalon® -ST is the fastest configuration scheme for Intel® Stratix® 10 devices. This scheme uses an external host, such as a microprocessor, MAX® II, MAX® V, or Intel® MAX® 10 device to drive configuration. The external host controls the transfer of configuration data from external storage such as flash memory to the FPGA. The logic that controls the configuration process resides in the external host. You can use the PFL II IP with a MAX® II, MAX® V, or Intel® MAX® 10 device as the host to read configuration data from the flash memory device and configure the Intel® Stratix® 10 device. The Avalon® -ST configuration scheme is called passive because the external host, not the Intel® Stratix® 10 device, controls configuration.

Table 12.   Avalon® -ST Configuration Data Width, Clock Rates, and Data RatesMbps is an abbreviation for Megabits per second.
Protocol Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Avalon® -ST 32 125 MHz 4000 Mbps 000
16 125 MHz 2000 Mbps 101
8 125 MHz 1000 Mbps 110
Table 13.  Required Configuration Signals for the Avalon® -ST Configuration Scheme You can use an 8-, 16-, or 32-bit Avalon-ST configuration data bus. You specify SDM I/O pin functions using the Device > Device and Pin Options > Configuration dialog box in the Intel® Quartus® Prime software. For the Avalon-ST x16 and x32 configuration, you can reassign the GPIO, dual-purpose configuration pins for other functions in user mode using the Device > Device and Pin Options > Dual-Purpose Pins dialog box.
Signal Name Pin Type Direction Powered by
nSTATUS SDM I/O Output VCCIO_SDM
nCONFIG SDM I/O Input VCCIO_SDM
MSEL[2:0] SDM I/O Input VCCIO_SDM
CONF_DONE 11 SDM I/O Output VCCIO_SDM
AVST_READY SDM I/O Output VCCIO_SDM
AVSTx8_DATA[7:0] SDM I/O Input VCCIO_SDM
AVSTx8_VALID SDM I/O Input VCCIO_SDM
AVSTx8_CLK SDM I/O Input VCCIO_SDM
AVST_DATA[31:0] GPIO, Dual-Purpose Input VCCIO
AVST_VALID GPIO, Dual-Purpose Input VCCIO
AVST_CLK GPIO, Dual-Purpose Input VCCIO

Refer to the Intel® Stratix® 10 Data Sheet for configuration timing estimates.

Note: Although the INIT_DONE configuration signal is not required for configuration, Intel recommends that you use this signal. The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode. This signal is important when debugging configuration.
Note: If you create custom logic instead of using the PFL II IP to drive configuration, refer to the Avalon Streaming Interfaces in the Avalon Interface Specifications for protocol details.
11 CONF_DONE is required if you are using the Intel FPGA Parallel Flash Loader II IP as the configuration host.

Did you find the information on this page useful?

Characters remaining:

Feedback Message