3.1.5. Avalon-ST Single-Device Configuration
Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements.
Notes for Figure:
- Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes.
- The synchronizers shown in all three figures can be internal if the host is an FPGA or CPLD. If the host is a microprocessor, you must use discrete synchronizers.
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