Intel® Stratix® 10 Configuration User Guide

Download
ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.1.5. Avalon-ST Single-Device Configuration

Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines for additional information about individual pin usage and requirements.

Figure 17. Connections for Avalon-ST x8 Single-Device Configuration
Figure 18. Connections for Avalon-ST x16 Single-Device Configuration
Figure 19. Connections for Avalon-ST x32 Single-Device Configuration

Notes for Figure:

  1. Refer to MSEL Settings for the correct resistor pull-up and pull-down values for all configuration schemes.
  2. The synchronizers shown in all three figures can be internal if the host is an FPGA or CPLD. If the host is a microprocessor, you must use discrete synchronizers.

Did you find the information on this page useful?

Characters remaining:

Feedback Message