5.3.1. Operation Commands
Resetting Quad SPI Flash
RSU SDM Command Use Case
|Command||Code (Hex)||Command Length 17||Response Length 17||Description|
Triggers reconfiguration from the data source that can be either the factory or an application image.
This command takes an optional 64-bit argument that specifies the reconfiguration data address in the flash. When sending the argument to the IP, you first send bits [31:0] followed by bits [63:32]. If you do not provide this argument its value is assumed to be 0.
Once the device processes this command, it returns the response header to response FIFO before it proceeds to reconfigure the device. Ensure the host PC or host controller stops servicing other interrupts and focuses on reading the response header data to indicate the command completed successfully. Otherwise, the host PC or host controller may not be able to receive the response once the reconfiguration process started.
Once the device proceeds with reconfiguration, the link between the external host and FPGA is lost. If you use PCIe in your design, you need to re-enumerate the PCIe link.
RSU_GET_SPT retrieves the quad SPI flash location for the two sub-partition tables that the RSU uses: SPT0 and SPT1.
The 4-word response contains the following information:
|0||SPT0[63:32]||SPT0 address in quad SPI flash.|
|2||SPT1[63:32]||SPT1 address in quad SPI flash.|
Reports the status of the last reconfiguration. You can use this command to check the configuration status during and after configuration. The response contains the following information:
|0||State||Describes the most recent configuration related error. Returns 0 when there are no configuration errors.
The error field has 2 fields:
Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide for more information.
Available in Intel® Quartus® Prime software version 19.4 or later, the field displays:
|3||Soft function status||Contains the value of each of the soft functions, even if you have not assigned the function to an SDM pin.
|4||Error location||Contains the error location. Returns 0 if there are no errors.|
|5||Error details||Contains the error details. Returns 0 if there are no errors.|
|RSU_STATUS||5B||0||9||Reports the current remote system upgrade status. You can use this command to check the configuration status during configuration and after it has completed. This command returns the following responses:|
|0-1||Current image||Flash offset of the currently running application image.|
Flash offset of the highest priority failing application image. If multiple images are available in flash memory, stores the value of the first image that failed. A value of all 0s indicates no failing images. If there are no failing images, the remainder of the remaining words of the status information do not store valid information.
Note: A rising edge on nCONFIG to reconfigure from ASx4, does not clear this field. Information about failing image only updates when the Mailbox Client receives a new RSU_IMAGE_UPDATE command and successfully configures from the update image.
|4||State||Failure code of the failing image.
The error field has two parts:
Returns 0 for no failures. Refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide for more information.
RSU interface version and error source.
For more information, refer to RSU Status and Error Codes section in the Hard Processor System Remote System Update User Guide.
|6||Error location||Stores the error location of the failing image. Returns 0 for no errors.|
|7||Error details||Stores the error details for the failing image. Returns 0 if there are no errors.|
|8||Current image retry counter||
Count of the number of retries that have been attempted for the current image. The counter is 0 initially. The counter is set to 1 after the first retry, then 2 after a second retry.
Specify the maximum number of retries in your Intel® Quartus® Prime Settings File (.qsf). The command is: set_global_assignment -name RSU_MAX_RETRY_COUNT 3. Valid values for the MAX_RETRY counter are 1-3. The actual number of available retries is MAX_RETRY -1
This field was added in version 19.3 of the Intel® Quartus® Prime Pro Edition software.
Clears all error information in the RSU_STATUS response and resets the retry counter. The one-word argument has the following fields:
This command is not available before version 19.3 of the Intel® Quartus® Prime Pro Edition software.
Requests exclusive access to the quad SPI. You issue this request before any other QSPI requests. The SDM accepts the request if the quad SPI is not in use and the SDM is not configuring the device. Returns OK if the SDM grants access.
The SDM grants exclusive access to the client using this mailbox. Other clients cannot access the quad SPI until the active client relinquishes access using the QSPI_CLOSE command.
Access to the quad SPI flash memory devices via any mailbox client IP is not available by default in designs that include the HPS, unless you disable the QSPI in HPS software configuration.
|QSPI_CLOSE||33||0||0||Closes the exclusive access to the quad SPI interface.|
|QSPI_SET_CS||34||1||0||Specifies one of the attached quad SPI devices via the chip select lines. Takes a one-word argument as described below:
Note: The HPS can use nCSO[3:1] to access 3 additional quad SPI devices.
This command is optional for the AS x4 configuration scheme, the chip select line follows the last executed QSPI_SET_CS command or defaults to nCSO after the AS x4 configuration. The JTAG configuration scheme requires executing this command to access the QSPI flash that connects the SDM_IO pins.
Access to the QSPI flash memory devices using SDM_IO pins is only available for the AS x4 configuration scheme, JTAG configuration, and a design compiled for AS x4 configuration. For the Avalon® streaming interface ( Avalon® ST) configuration scheme, you must connect QSPI flash memories to GPIO pins.
Reads the attached quad SPI device. The maximum transfer size is 4 kilobytes (KB) or 1024 words.
Takes two arguments:
For a partially successful read, QSPI_READ may erroneously return the OK status.
Note: You cannot run the QSPI_READ command while device configuration is in progress.
Writes data to the quad SPI device. The maximum transfer size is 4 kilobytes (KB) or 1024 words.
Takes three arguments:
To prepare memory for writes, use the QSPI_ERASE command before issuing this command.
Note: You cannot run the QSPI_WRITE command while device configuration is in progress.
|QSPI_ERASE||38||2||0||Erases a 4/32/64 KB sector of the quad SPI device. Takes two arguments:
|QSPI_READ_DEVICE_REG||35||2||N||Reads registers from the quad SPI device. The maximum read is 8 bytes. Takes two arguments:
A successful read returns the OK response code followed by the data read from the device. The read data return is in multiple of 4 bytes. If the bytes to read is not an exact multiple of 4 bytes, it is padded with multiple of 4 bytes until the next word boundary and the padded bit value is zero.
|QSPI_WRITE_DEVICE_REG||36||2+N||0||Writes to registers of the quad SPI. The maximum write is 8 bytes. Takes three arguments:
To perform a sector erase or sub-sector erase, you must specify the serial flash address in most significant byte (MSB) to least significant byte (LSB) order as the following example illustrates.
To erase a sector of a Micron 2 gigabit (Gb) flash at address 0x04FF0000 using the QSPI_WRITE_DEVICE_REG command, write the flash address in MSB to LSB order as shown here:
Number of bytes to write: 0x00000004
Flash address: 0x0000FF04
A successful write returns the OK response code. This command pads data that is not a multiple of 4 bytes to the next word boundary. The command pads the data with zero.
|QSPI_SEND_DEVICE_OP||37||1||0||Sends a command opcode to the quad SPI. Takes one argument:
A successful command returns the OK response code.
For CONFIG_STATUS and RSU_STATUS major and minor error code descriptions, refer to Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions in the Mailbox Client Intel® FPGA IP User Guide .
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