Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)

The partial reconfiguration signals use GPIO pins.

The following signals control partial reconfiguration in Intel® Stratix® 10 devices:

  • PR_REQUEST
  • PR_READY
  • PR_ERROR
  • PR_DONE

Connect these partial reconfiguration signals to the Partial Reconfiguration External Configuration Controller Intel® FPGA IP.

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