Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 5/30/2022
Public
Document Table of Contents

3.2. AS Configuration

In AS configuration schemes, the SDM block in the Intel® Stratix® 10 device controls the configuration process and interfaces. The serial flash configuration device stores the configuration data. During AS Configuration, the SDM first powers on with the boot ROM. Then, the SDM loads the initial configuration firmware from AS x4 flash. After the configuration firmware loads, this firmware controls the remainder of the configuration process, including I/O configuration and FPGA core configuration. Designs including an HPS, can use the HPS to access serial flash memory after the initial configuration.

Note: The serial flash configuration device must be fully powered up at the same time or before ramping up VCCIO_SDM of the Intel® Stratix® 10 device. For more information about the power sequence, refer to the Intel® Stratix® 10 Power Management User Guide.
Important: Do not reset the quad SPI flash when used as the configuration device and data storage device with FPGA. Resetting the quad SPI flash during the FPGA configuration and reconfiguration, or in the QSPI's READ/WRITE/ERASE operations, causes undefined behavior for quad SPI flash and the FPGA. To recover from the unresponsive behavior, you must power cycle your device. To reset the quad SPI flash via the external host, you must first complete the FPGA configuration and reconfiguration, or a quad SPI operation, and only then toggle the reset. The quad SPI operation is complete when the exclusive access to the quad SPI flash is closed by issuing the QSPI_CLOSE command via the Mailbox Client Intel® FPGA IP or CLOSE command via the Serial Flash Mailbox Client Intel® FPGA IP.

The AS configuration scheme supports AS x4 (4-bit data width) mode only.

Table 28.   Intel® Stratix® 10 Configuration Data Width, Clock Rates, and Data Rates
Mode Data Width (bits) Max Clock Rate Max Data Rate MSEL[2:0]
Active Active Serial (AS)

4

125 MHz 500 Mbps

Fast mode - 001

Normal mode - 011

Table 29.  Required Configuration Signals for the AS Configuration Scheme
Configuration Function Pin Type Direction Powered by
nSTATUS SDM I/O Output VCCIO_SDM
nCONFIG SDM I/O Input VCCIO_SDM
MSEL[2:0] SDM I/O Input VCCIO_SDM
AS_nCSO[3:0] SDM I/O Output VCCIO_SDM
AS_DATA[3:0] SDM I/O Bidirectional VCCIO_SDM
AS_CLK SDM I/O Output VCCIO_SDM
Note: Although the CONF_DONE and INIT_DONE configuration signals are not required, Intel recommends that you use these signals. The SDM drives the CONF_DONE signal high after successfully receiving full bitstream. The SDM drives the INIT_DONE signal high to indicate the device is fully in user mode.These signals are important when debugging configuration.

MSEL Pin Function for the AS x4 Configuration Scheme

The SDM samples the MSEL pins immediately after power-on in the SDM Start state. After the SDM samples the MSEL pins, the MSEL pins become active-low chips selects. For AS x4 designs using one flash device, AS_nCSOO asserts low when the SDM starts to communicate with the QSPI flash. The remaining chip select pins, AS_nCSO1 - AS_nCSO3 deassert high.

Note: MSEL[0] and AS_nCSOO pins share the same SDM I/O. Refer to SDM Pin Mapping for more details.

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