3.2.7. Serial Flash Memory Layout
Serial flash devices store the configuration data in sections. The first stage boot loader location depends on the selected serial flash memory layout.
Non-HPS Case:
The following diagram illustrates sections of a non-HPS Stratix® 10 configuration data mapping in a serial flash device. The non-HPS bitstreams do not include first stage boot loader (FSBL). Refer to Stratix® 10 SoC FPGA Bitstream Sections of the HPS Technical Reference Manual for more information about flash memory layout for HPS devices.
HPS Case with FPGA First Option:
HPS Case with HPS First Option and Dual Flash:
If you use a third-party programmer to program an .rpd, ensure that the configuration data is stored starting from address 0 of the serial flash device. If you use .jic or .pof files, the Stratix® 10 Programmer automatically programs the configuration data starting from address 0 of the serial flash device.
Altera currently support the following listed Supported Flash Devices for Stratix® 10