184.108.40.206.2. Implementing Multiple Pages in the Flash .pof
The total number of pages and the size of each page depends on the flash density. Here are some guidelines for storing your designs to pages:
- Always store designs for different FPGA chains on different pages.
- You may choose store different designs for a FPGA chain on a single page or on multiple pages.
- When you choose to store the designs for a FPGA chain on a single page, the design order must match the JTAG chain device order.
Use the generated .sof to create a flash memory device .pof. The following address modes are available for the .sof to .pof conversion:
- Block mode—allows you to specify the start and end addresses for the page.
- Start mode—allows you to specify only the start address. The start address for each page must be on an 8 KB boundary. If the first valid start address is 0×000000, the next valid start address is an increment of 0×2000.
- Auto mode—allows the Intel® Quartus® Prime software to automatically determine the start address of the page. The Intel® Quartus® Prime software aligns the pages on a 128 KB boundary. If the first valid start address is 0x000000, the next valid start address is an multiple of 0x20000.
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