Device Family: Intel® Stratix® 10

Type: Answers

Area: Component


Last Modified: August 20, 2018
Bug ID: FB: 514261;

Should clocks and resets in user logic be gated until the configuration process is completed in Intel® Stratix® 10 devices?

Description

After the Intel® Stratix® 10 device completes configuration and enters user mode, you are required to implement a reset sequence before running your application. On the completion of the configuration stage, the functions of the Intel Stratix 10 device are not expected to come into user mode simultaneously. When the device enters into user mode, a free running clock might cause a clock race condition between user logics that corrupts the device initial conditions.

Workaround/Fix

To prevent this event, Intel recommends that you build a design using the User Reset and Clock Gate Intel Stratix 10 FPGA IP working with your own user logic to un-gate the User Clock and de-assert the Global Reset signal as shown in the block diagram below. Use the User Reset and Clock Gate Intel Stratix 10 FPGA IP core to de-assert the signal from user_reset port to un-gate the User Clock. Then build your own logic to de-assert the Global Reset signal after you have un-gate the User Clock.

Note that the 'Free Running Clock' is an externally sourced clock, whilst the ‘User Clock’ is a clock that clocks user logic in the FPGA. The User Clock could also be a free running clock or a PLL generated clock.

It is expected that only a single IP instance is required to ungate all user clocks, whilst the global reset signal should be used to release/de-assert the reset in multiple domains. If the design has multiple reset domains, ensure the global reset signal is held long enough for the signal to propagate to all the domains before de-asserting it. 

User Reset and Clock Gating Block Diagram

Note(1): Do not use the user_clkgate port of the User Reset and Clock Gate Intel Stratix 10 FPGA IP.

Following are the recommended de-assertion delay for user_reset signal by using the Intel FPGA Stratix 10 User Reset and Clock Gate IP and the de-assertion delay for Global Reset signal.  

The user_reset signal de-assertion delay must be more than one User Clock cycle. You can get the desired delay by entering the De-assertion Delay value in the User Reset and Clock Gate Intel Stratix 10 FPGA IP. The possible values for the De-assertion Delay parameter in the User Reset and Clock Gate Intel Stratix 10 FPGA IP can range from 0 ns to 65535 ns. You must build a synchronizer using standard anti-metastable technique inside:

a) the “User Logic to Ungate User Clock” to synchronize the user_reset signal with respect to the free running clock

b) the “User Logic to De-assert Global Reset” to synchronize the user_reset signal with respect to User Clock

The Global Reset signal de-assertion delay must be long enough for the Global Reset signal to propagate to the global reset logic in your system after User Clock is running. Build your own user logic to de-assert the Global Reset signal after user_reset is de-asserted and User Clock is running. You must also synchronize the Global Reset signal with respect to User Clock using standard anti-metastable techniques. 

User Reset and Clock Gating Timing Diagram

This information will be documented in the future release of Intel Stratix 10 Configuration User Guide.