Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.2.9.1.1. Monitors for Mutual Exclusion

The SDRAM scheduler implements support for mutually-exclusive (mutex) accesses on all ports to the SDRAM L3 interconnect.

The process for a mutually-exclusive access is as follows:

  1. A master attempts to lock a memory location by performing an exclusive read from that address.
  2. The master attempts to complete the exclusive operation by performing an exclusive write to the same address location.
  3. The exclusive write access is signaled as:
    • Failed if another master has written to that location between the read and write accesses. In this case the address location is not updated.
    • Successful otherwise.

To support mutually-exclusive accesses from the MPU, the memory must be configured in the MMU page tables as normal memory, shareable, or non-cacheable.