Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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16.2. Quad SPI Flash Controller Block Diagram and System Integration

Figure 82. Quad SPI Flash Controller Block Diagram and System Integration

The quad SPI controller consists of the following blocks and interfaces:

  • Register slave interface - Provides access to the control and status registers (CSRs)
  • Data slave controller - Interface and controller that provides the following functionality:
    • Performs data transfers to and from the level 3 (L3) interconnect
    • Validates incoming accesses
    • Performs byte or half-word reordering
    • Performs write protection
    • Forwards transfer requests to direct and indirect controller
  • Direct access controller - provides memory-mapped slaves direct access to the flash memory
  • Indirect access controller - provides higher-performance access to the flash memory through local buffering and software transfer requests
  • Software triggered instruction generator (STIG) - generates flash commands through the flash command register (flashcmd) and provides low-level access to flash memory
  • Flash command generator - generates flash command and address instructions based on instructions from the direct and indirect access controllers or the STIG
  • DMA peripheral request controller - issues requests to the DMA peripheral request interface to communicate with the HPS DMA controller
  • SPI PHY - serially transfers data and commands to the external SPI flash devices

The static RAM (SRAM) connected to the indirect access controller, DMA peripheral request controller, and data slave controller has an error correction code (ECC) controller built-in to provide ECC protection. The ECC controller is able to detect single-bit and double-bit errors, and correct the single-bit errors. The ECC operation and functionality is programmable via the ECC register slave interface, as shown in Figure 82. The ECC register interface provides host access to configure the ECC logic as well as inject bit errors into the memory. It also provides host access to memory initialization hardware used to clear out the memory contents including the ECC bits. The ECC controller generates interrupts upon occurrences of single and double-bit errors, and the interrupt signals are connected to the system manager.