Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

A.4.6.1. I/O State

The state of the device I/O pins changes depending on the current operation mode of the device. The table below describes the changes in state per I/O type for each operating mode of the device.
Table 323.  I/O State
I/O Type Operation Modes from the time the FPGA is Unconfigured (POR) to User Mode Operation Modes after the FPGA is Configured
Power up HPS Boot ROM Mode Early I/O Release Mode User Mode HPS Cold Reset FPGA Partial Reconfiguration FPGA Full Reconfiguration
Dedicated HPS I/O used during Boot Input tri-state Select I/O are configured by Boot ROM; unused I/O remain as input tri-state. Select I/O are configured by software. Unused I/O remain as input tri-state. Select I/O are configured by software. Unused I/O remain as input tri-state. Input tri-state Configured I/O continue to operate. Unused I/O remain as input tri-state. Configured I/O continue to operate. Unused I/O remain as input tri-state.
HPS Shared I/O Input tri-state 63 Input tri-state unless FPGA is being configured. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Pin multiplexer is reset and thus I/O pins can be input tri-state. Configured I/O continue to operate. Unused I/O remain as input tri-state. When full reconfiguration begins, I/O state reverts to input tristate. Once configuration is complete, unused I/O remain as input-tristate while selected I/O are configured by bitstream.
Note: In this mode, any HPS peripheral connected to the shared I/O loses connectivity until configuration is complete.
HPS DDR I/O Input tri-state63 Input tri-state unless FPGA is being configured. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Configured I/O continue to operate. Configured I/O continue to operate. Unused I/O remain as input tri-state. When full reconfiguration begins, I/O state reverts to input tristate. Once configuration is complete, unused I/O remain as input-tristate while selected I/O are configured by bitstream.
Note: In this mode HPS loses connectivity to HPS DDR and may need to be reset to reboot the system.
FPGA I/O Input tri-state63 Input tri-state unless FPGA is being configured. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Select I/O are configured by configuration bitstream. Unused I/O remain as input tri-state. Configured I/O continue to operate. Configured I/O continue to operate. Unused I/O remain as input tri-state. When full reconfiguration begins, I/O state reverts to input tristate. Once configuration is complete, unused I/O remain as input-tristate while selected I/O are configured by bitstream.
63 Depending on the nIO_PULLUP pin value, the weak pull up of the pins may be enabled.