Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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3.3.1.2. FREF, FVCO, and FOUT Equations

Figure 5. PLL Block Diagram

Values listed for M, N, and C are actually one greater than the values stored in the CSRs.


FREF = FIN / N
FVCO = FREF × M = FIN × M/N
FOUT = FVCO /Ci = FREF × M/Ci = (FIN × M)/ (N × Ci)

where:

  • FVCO = VCO frequency
  • FIN = input frequency
  • FREF = reference frequency
  • FOUT = output frequency
  • M = numerator, part of the clock feedback path
  • N = denominator, part of the input clock reference path
  • Ci = post-scale counter, where i is 0-8

The Ci dividers are used to derive lower frequencies from the PLLs. The M and N dividers can be dynamically updated without losing the PLL lock if the VCO frequency changes less than 20%. If changes greater than 20% are needed, iteratively changing the frequency in increments of less than 20% allows a slow ramp of the VCO frequency without loss of clock.

To minimize jitter, use the following guidelines:

  • The VCO should be as close to maximum as possible
  • It is better to use the Ci dividers than the N divider. The N divider should be kept as small as possible.
  • The M divider should be minimized, but should be greater than 32.

When making any changes that affect the VCO frequency, software must put the PLL into external bypass. After changing the VCO frequency, software must wait for the PLL lock, as indicated by the intrs register or enabled interrupt, before taking the PLL out of bypass.

As shown in the "Hardware Clock Groups" and "Peripheral Clocks" figures, every clock has five possible sources. When switching between clock sources:

  • Put PLL into bypass mode
  • Change the mux select
  • Switch back out of bypass mode
    Note: The new clock source must be active and locked before exiting bypass mode.

As shown in the "PLL Integration in Clock Manager" figure, each PLL has multiple input sources. If the input source is changed, the PLL loses VCO lock and all output clocks are not reliable. Before switching the PLL input source, software must select the boot_clk bypass for all PLL0 and PLL1 clocks. After the PLL output clocks are bypassed, software can change the PLL source and reinitialize the PLL.

Unused clock outputs should be set to a safe frequency such as 50 MHz to reduce power consumption and improve system stability.