Intel® Arria® 10 Hard Processor System Technical Reference Manual
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11.4.1. Debug Access Port
The Debug Access Port (DAP) provides the necessary ports for a host debugger to connect to and communicate with the HPS through a JTAG interface, which is connected to the FPGA JTAG chain. The JTAG interface provided with the DAP allows a host debugger to access various modules inside the HPS. Additionally, a debug monitor executing on either processor can access different HPS components by interfacing with the system Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced Peripheral Bus ( APB* ) slave port of the DAP.
The system APB* slave port occupies 2 MB of address space in the HPS. Both the JTAG port and system APB* port have access to the debug APB* master port of the DAP.
A host debugger can access any HPS memory-mapped resource in the system through the DAP system master port. Requests made over the DAP system master port are impacted by reads and writes to peripheral registers.