Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2.4.1. Arria 10 HPS SDRAM L3 Interconnect

The SDRAM L3 interconnect is part of the system interconnect and connects the HPS to the hard memory controller that is located in the FPGA fabric. The SDRAM L3 interconnect is composed of the SDRAM adapter and the SDRAM scheduler, which are secured by firewalls. It supports Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) quality of service (QoS) for the fabric interfaces

The hard memory controller implements the following high-level features:

  • Support for double data rate 3 (DDR3) and DDR4 devices
  • Software-configurable priority scheduling on individual SDRAM bursts
  • Error correction code (ECC) support, including calculation, single‑bit error correction and write-back, and error counters
  • Fully-programmable timing parameter support for all JEDEC‑specified timing parameters
  • All ports support memory protection and mutual-exclusive accesses
  • FPGA-to-SDRAM interface—a configurable interface to the SDRAM scheduler in the SDRAM L3 interconnect You can configure the following parameters:
    • Up to three bridges
    • Up to 288 bits across all three ports