Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

11.1. Features of CoreSight* Debug and Trace

The CoreSight* debug and trace system offers the following features:

  • Real-time program flow instruction trace through a separate Program Trace Macrocell (PTM) for each processor
  • Host debugger JTAG interface
  • Connections for cross-trigger and STM-to-FPGA interfaces, which enable soft IP generation of triggers and system trace messages
  • External trace interface through Trace Port Interface Unit (TPIU) for trace analysis tools
  • Custom message injection through the System Trace Macrocell (STM) into the trace stream for delivery to a host debugger
  • STM, PTM, and level 3 (L3) trace sources multiplexed into a single stream through the Trace Funnel
  • Capability to route trace data to any slave accessible to the Embedded Trace Router (ETR) AXI master connected to the L3 interconnect
  • Capability for the following components to trigger each other through the embedded cross-trigger system:
    • Cortex*-A9 PTM-0
    • Cortex*-A9 PTM-1
    • STM
    • Embedded Trace FIFO (ETF)
    • ETR
    • TPIU
    • Cross Trigger Interface (CTI)
    • FPGA‑CTI
    • Cross Trigger Matrix (CTM)