Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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11.5.2. STM Channels

The STM AXI slave is connected to the MPU, DMA, and FPGA-to-HPS bridge masters. Each master has up to 65536 channels where each channel occupies 256 bytes of address space, for a total of 16 MB per master. The HPS address map allocates 48 MB of consecutive address space to the STM AXI slave port, divided in three 16 MB segments.

Table 105.  STM AXI Slave Port Address Allocation

Segment

Start Address

End Address

0

0xFC000000

0xFCFFFFFF

1

0xFD000000

0xFDFFFFFF

2

0xFE000000

0xFEFFFFFF

Each of the three masters can access any one of the three address segments. Your software design determines which master uses which segment, based on the value of bits 24 and 25 in the write address, AWADDRS[25:24]. Software must restrict each master to use only one of the three segments.

Table 106.  STM AXI Address Fields

STM receives trace data over an AXI slave port. This table contains a list of signals associated with this interface.

AXI Signal Fields

Description

AWADDRS[7:0]

These bits index the 256 bytes of the stimulus port.

AWADDRS[23:8]

These bits identify the 65536 stimulus ports associated with a master.

AWADDRS[25:24]

These bits identify the three masters. Only 0, 1, and 2 are valid values.

AWADDRS[31:26]

Always 0x3F. Bits 24 to 31 combine to access 0xFC000000 through 0xFEFFFFFF.

Each STM message contains a master ID that tells the host debugger which master is associated with the message. The STM master ID is determined by combining a portion of the AWADDRS signal and the AWPROT protection bit. In the following table, MasterID[6] identifies the

Table 107.  STM Master ID Calculation

Master ID Bits

AXI Signal Bits

Notes

Master ID[5:0]

AWADDRS[29:24]

The lowest two bits are sufficient to determine which master, but CoreSight uses a six-bit master ID.

Master ID[6]

AWPROT[1]

0 indicates a secure master; 1 indicates a nonsecure master.

In addition to access through STM channels, the higher-order 28 (31:4) of the 32 event signals are attached to the FPGA through the FPGA‑CTI. These event signals allow the FPGA fabric to send additional messages using the STM.