Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

26.1. Features of the HPS I/O Block

The I/O block provides the following functionality and features:

  • I/O pins
    • Dedicated I/O: 17 pins supporting clock, resets, boot devices, and other key peripherals. These pins cannot be used by soft logic in the FPGA.
    • Shared I/O: 48 pins available for HPS external memory and peripherals. Shared I/O pins can also be used by FPGA logic.
    Note: The HPS also interfaces with an SDRAM memory controller. This interface is separate from the dedicated and shared I/O pins discussed in this chapter.
  • I/O multiplexing
    • Selects pins used by each HPS peripheral
    • Can assign shared I/O pins to FPGA logic
    • Can expose HPS peripheral interfaces to FPGA logic
      Note: When routed to the FPGA, some HPS peripherals require additional pipeline support in the connected soft logic. Refer to the relevant HPS peripheral chapter for details.

    I/O multiplexing is configured when you instantiate the HPS component.