Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

1. Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History

Updated for:
Intel® Quartus® Prime Design Suite 21.2
Table 1.   Intel® Arria® 10 Hard Processor System Technical Reference Manual Revision History Summary
Chapter Date of Last Update
Introduction to the Hard Processor System August 22, 2022
Clock Manager July 22, 2017
Reset Manager July 22, 2017
FPGA Manager November 2, 2015
System Manager May 27, 2016
SoC Security February 23, 2018
System Interconnect January 21, 2021
HPS-FPGA Bridges July 22, 2017
Cortex*-A9 Microprocessor Unit Subsystem Revision History May 26, 2021
CoreSight* Debug and Trace July 29, 2017
Error Checking and Correction Controller November 2, 2015
On-Chip Memory August 18, 2014
NAND Flash Controller November 14, 2022
SD/MMC Controller July 8, 2021
Quad SPI Flash Controller August 18, 2020
DMA Controller July 22, 2017
Ethernet Media Access Controller August 22, 2022
USB 2.0 OTG Controller November 2, 2015
SPI Controller November 2, 2015
I2C Controller November 2, 2015
UART Controller November 2, 2015
General-Purpose I/O Interface December 15, 2014
Timer August 18, 2014
Watchdog Timer November 2, 2015
Hard Processor System I/O Pin Multiplexing June 14, 2019
Introduction to the HPS Component May 3, 2016
Instantiating the HPS Component January 10, 2023
HPS Component Interfaces May 27, 2016
Simulating the HPS Component May 27, 2016
Booting and Configuration July 22, 2017

Document Version

Changes

2022.08.22 Removed RGMII because it does not support FPGA IO
2017.05.31 Removed HMCREGS row from HPS Peripheral Region Map table. Accesses to this address block are not supported.
2016.10.28 Renamed MPU Subsystem to Cortex*-A9 MPCore*
2016.05.27 Corrected the HPS-FPGA powering scheme.

2016.05.03

Removed low-power double data rate 3 (LPDDR3) as a supported device.
2015.11.02 Updated the link to the Memory Maps.
2015.05.04 Corrected HPS-FPGA powering scheme.
2014.12.15 Maintenance release
2014.08.18

Initial release

Introduction to the Hard Processor System
Document Version Changes
2017.07.22
  • Replaced instances of EOSC1 pin with correct pin name, HPS_CLK1.
  • Clarified that the osc1_clk signal is sourced from the HPS_CLK1 input pin.
2016.10.28
  • Added mpuclk register (offset 0x0) to i_clk_mgr_alteragrp
2016.05.27
  • Removed references to f2h_emac*_ap_clk in the Arria 10 Top Level Clocks table. The Ethernet application interface (also called the switch interface) is not supported.
  • Removed clk9cntr (offset 0x44) and clk15cntr (offset 0x5C) registers from the i_clk_mgr_mainpllgrp
  • Removed clk9cntr register (offset 0x44) from the i_clk_mgr_perpllgrp
  • Clarified the src fields of the clk*cntr registers in the i_clk_mgr_mainpllgrp and i_clk_mgr_perpllgrp
Removed references to PLL counter outputs C9-C15 from the following topics:
  • Boot Clock
  • PLLs
  • FREF, FVCO, and FOUT Equations
2016.05.03 Added a section titled "L4 Peripheral Clocks".
2015.11.02 Updated Sections:
  • Clock Manager Block Diagram and System Integration
  • PLL Integration
  • Software Sequenced Clocks
  • Clock Gating
  • Boot Clock

Added Sections:

  • Updating PLL Settings without a System Reset
  • MPU Clock Scaling

Updates:

  • Removed references to PLL output C9 used as HMC PLL reference clock.
2015.05.04
  • Updated Block Diagram with HMC block
  • Added Arria 10 Top Level Clocks table
  • Updated PLL Integration in Clock Manager figure
  • Added Address Map and Register Descriptions
2014.12.15

Clock Manager Block Diagram. Updated mux output route. NOC clock added. Peripheral Clocks block update

C15 input for PLL1 has been removed throughout document.

2014.08.18 Initial release.
Clock Manager
Document Version Changes
2017.07.22
  • Removed references to EOSC1 and replaced them with the correct external oscillator pin name, HPS_CLK1.
  • Clarified that the osc1_clk signal is sourced from the HPS_CLK1 pin.
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02 Updated "Reset Pins" section.
2015.05.04 "Slave Interface" and "Status Register" sections updated.
2014.12.15 Maintenance release.
2014.08.18 Initial release.
Reset Manager

Document Version

Changes

2015.11.02
  • Provided more information for the configuration schemes for the dedicated pins.
  • Added missing address maps and register definitions.
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.08.18 Initial release
FPGA Manager
Document Version Changes
2016.10.28 Maintenance release.
2016.05.27 Removed the following references to the Ethernet application interface:
  • app_clk_sel content in the EMAC section
  • emac_*_switch bits in the fpgaintf_en_3 register
  • app_clk_sel bits in the emac* registers
The Ethernet application interface (also called the switch interface) is not supported.
2016.05.03 Maintenance release.
2015.11.02 Maintenance release.
2015.05.04 Maintenance release.
2014.12.15
  • Block Diagram updated: Slave port defined
  • "NAND Flash Controller" section updated
  • "USB 2.0 OTG" section updated
  • "EMAC" section updated
2014.08.18 Initial release.
System Manager
Table 2.  SoC Security Revision History
Date Version Changes
July 2017 2017.07.21
  • Removed references to EOSC1 and replaced them with the correct external oscillator pin name, HPS_CLK1.
  • Clarified that the osc1_clk signal is sourced from the HPS_CLK1 pin.
October 2016 2016.10.28 Maintenance release
May 2016 2016.05.27 Maintenance release
May 2016 2016.05.03
  • Added note regarding blocked firewall transaction responses in the "Secure Firewall" section
  • Updated content and added figures to "JTAG" section
November 2015 2015.11.02 Clarified initialization steps in "Secure Initialization Overview" section
May 2015 2015.05.04 Added Address Map and Register information.
December 2014 2014.12.15
  • Added "Secure Fuses" section under "Secure Initialization" section.
  • Added summary of "Security State" and "Security Check" and "Secure Serial Interface" features.
  • Added "MPU" and "JTAG" sub-sections to the "Secure Debug" section.
  • Added information regarding CSEL programming in the "Clock Configuration" section.
  • Added "FPGA Security Features" section
August 2014 2014.08.18 Initial Release
unresolvable-reference.html
Table 3.  System Interconnect Revision History

Document Version

Changes

2021.01.21 Updated Arria 10 HPS Available Address Maps to explain how to access the registers that are connected to the HPS-to-FPGA AXI* Master Bridge.
2019.01.01 Updated ddrConf bitfield description in the ddr_T_main_Scheduler_Ddrconf register to include encodings.
2018.09.24 Updated the following section:
  • ECC Read Behavior
2017.05.31
  • Clarify relationship between quality of service (QoS) and arbitration
  • Add QoS examples
  • Remove 32-bit bus from L3 interconnect to hard memory controller in the SDRAM L3 Interconnect Block Diagram and System Integration section.
  • Remove Hard Memory Controller Memory Mapped Registers section
  • Remove io48_hmc_mmr Address map and registers from System Interconnect Address Map and Register Definitions section
2016.10.28
  • "System Interconnect Slave Interfaces" table: Corrected acceptance values for Lightweight HPS-to-FPGA Bridge and Lightweight HPS-to-FPGA Bridge
  • "Controlling Quality of Service from Software": Added note about register access
  • "Configuring SDRAM Burst Sizes": Refers to guidelines for selecting burst sizes
  • "Sharing I/O between the EMIF and the FPGA": New section, discusses constraints on sharing I/Os with EMIF
2016.05.27 Maintenance release
2016.05.03 Maintenance release
2015.11.02
  • Correct size of HPS-to-FPGA region in "MPU Address Space"
  • Clarify power domains in "Functional Description of the SDRAM L3 Interconnect"
2015.05.04
  • Added address maps and register definitions
  • Added information about the SDRAM scheduler
  • Added information about rate adapters
  • Added information about the observation network
2014.12.15
  • Added register details for address remapping
  • Added information about quality of service
  • Added information about arbitration
  • Clarified block diagram of SDRAM L3 interconnect
2014.08.18 Initial release
unresolvable-reference.html
Document Version Changes
2017.07.22 Added note about bridge transaction timeout to "HPS-to-FPGA Bridge Clocks and Resets" and "Lightweight HPS-to-FPGA Bridge Clocks and Resets".
2016.10.28
  • Added note about AXI* 4 KB boundary restriction
  • Clarified description of bridge master-slave connections
2016.05.27 Maintenance release
2015.11.02 Maintenance release
2015.05.04 Added address maps and register definitions
2014.12.15 Maintenance release

2014.08.18

Initial release.

HPS-FPGA Bridges

Document Version

Changes

2021.05.26 Added clarification for ACP usage requirements by adding the following chapters:
  • AxPROT Attributes
  • Configuring AxPROT[2:0] Sideband Signals for Coherent Accesses
2020.08.18 Added information about maintaining cache coherency in the Accelerator Coherency Port
2019.06.14 Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,
2016.10.28
  • Added "Configuring AxCACHE[3:0] Sideband Signals" and "Configuring AxUser[4:0] Sideband Signals" subsections to the " AXI* Master configuration for ACP Access" section
2016.05.27 Maintenance release
2016.05.03 Maintenance release
2015.11.02
  • Reordered "L2 Cache" subsections
  • Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection"
  • Added "L2 Cache Parity" subsection in "L2 Cache" section
2015.05.04
  • Corrected allowed AxID values in "Accelerator Coherency Port" section
  • Added address maps for the Cortex*-A9 MPU subsystem and the L2 cache controller
2014.12.15
  • Added bus transaction scenarios in the "Accelerator Coherency Port" section
  • Added the "AxUSER and AxCACHE" subsection to the "Accelerator Coherency Port" section
  • Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port" section
  • Added the "Configuration for ACP Use" subsection to the "Accelerator Coherency Port" section
  • Added parity error handling information to the "L1 Caches" section and the "Cache Controller Configuration" topic of the "L2 Cache" section.
2014.08.18

Initial Release

Cortex-A9 Microprocessor Unit Subsystem

Document Version

Changes

2017.07.29 Added reset requirement for BST
2016.10.28 Maintenance release
2016.05.03 Maintenance release
2015.11.02 Added a description on how the 2 TAP controllers are connected and supporting figures.
2014.05.04 Maintenance release.
2014.12.15 Maintenance release.

2014.08.18

Initial release.

CoreSight Debug and Trace
Table 4.  Error Checking and Correction Controller Revision History
Date Version Changes
October 2016 2016.10.28 Maintenance Release
May 2016 2016.05.27 Maintenance Release
May 2016 2016.05.03 Maintenance Release
November 2015 2015.11.02
  • Added "ECC Bits Required Based on Data Width" table to "Error Checking and Correction Algorithm" section
  • Added 136-bit Hamming Matrix figure to "Error Checking and Correction Algorithm" section
May 2015 2015.05.04
  • Added 35-bit Hamming Matrix figure to "Error Checking and Correction Algorithm" section
  • Added "ECC Controller Address Map and Register Definitions" section
December 2014 2014.12.15

Added the "RAM and ECC Memory Organization Example" subsection to the "ECC Structure" section

Added the following subsections in the "Indirect Memory Access" section:

  • "Watchdog Timer"
  • "Data Correction"
  • "Error Injection"
  • "Memory Testing"
  • "Error Checking and Correction Algorithm"
August 2014 2014.08.18 Initial Release
Error Checking and Correction Controller

Document Version

Changes

2014.08.18 Initial release
On-Chip Memory

Document Version

Changes

2016.05.27 Added a link to the Supported Flash Devices for Arria 10 SoC webpage.

2016.05.03

Added information about determining how many CE/RB signals are available based on the selected pins.
2015.11.02
  • Updated the Interrupt and DMA Enabling section to recommend reading back a register to ensure clearing an interrupt status.
  • Removed the reference to a missing figure from the cs_setup_cnt description.
  • Documented the behavior of the wp_n bit for when it is or is not be available.
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release

2014.08.18

Initial release

NAND Flash Controller
Document Version Changes
2021.07.08 Changed the SD Card Clock Frequency in Changing the Card Clock Frequency.
2017.07.22 Corrected the MMC Support Matrix table in the "MMC Support Matrix" section.
2016.10.28 Removed SPI support in tables in the Features section.
2016.05.27 Added a link to the Supported Flash Devices for Arria 10 SoC webpage.
2016.05.03 Maintenance release
2015.11.02
  • Moved "Interface Signals" section below "SD/MMC Controller Block Diagram and System Integration" section and renamed to "SD/MMC Signal Description." Clarified signals in this section.
  • Removed the indication that the AV/CV HPS support 8-bit eMMC.
  • Added information that Card Detect is only supported on interfaces routed via the FPGA fabric.
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release
2014.08.18 Initial release
SD/MMC Controller
Document Version Changes
2020.08.18 Added clarification to the description of the QSPI register, indaddrtrig
2019.07.09 Added a new section, Write Request, with WREN and RDSR information
2019.06.14 Maintenance release
2016.10.28 Maintenance release
2016.05.27
  • Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.
  • Added a link to the Supported Flash Devices for Arria 10 SoC webpage.
  • Re-worded information about disabling the watermark feature in the "Indirect Read Operation" and "Indirect Write Operation" sections.
2016.05.03 Maintenance release
2015.11.02
  • Renamed "Interface Pins" section to "Quad SPI Flash Controller Signal Description" and moved it below the "Quad SPI Flash Controller Block Diagram and System Integration" section
  • Corrected the link to the HPS Address Map.
  • Added the Intel® Arria® 10 register map.
  • Better defined l4_main_clk clock.
  • Added Clock Gating information.
2015.05.04 Added information about clearing out the ECC before the feature is enabled
2014.12.15 Maintenance release
2014.08.18 Initial release
Quad SPI Flash Controller
Document Version

Changes

2017.07.22 Added information about DMA requiring that caches need to be enabled
2016.10.28 Maintenance release
2016.05.27 Maintenance release
2016.05.03 Maintenance release
2015.11.02
  • Updated link point to the HPS Address Map and Register Definitions
  • Added information about the instruction fetch cache properties
2015.05.04
  • Added Synopsys* handshake rules.
2014.12.15

Maintenance release

2014.08.18 Initial release
DMA Controller
Document Version Changes
2022.08.22 Removed RGMII because it does not support FPGA IO
2021.04.09 Added emac_clk_tx_i handling requirement for exported HPS EMAC GMII interface in the EMAC FPGA Interface Initialization section.
2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks after bringing the Ethernet PHY out of reset.
2019.06.14
  • Clarified the PCF bit description for encoding value 0x2 in the MAC_Frame_Filter register.
  • Clarified "Busy Bit" (gb bit of GMII_Address register) in Flow_Control register description.
  • Clarified that ttc bit resides in the Operation_Mode Register (Register 6).
  • Clarified that the pcsancis and the pcslchgis bits of theInterrupt_Status register can be ignored because they apply to TBI, RTBI, or SGMII interface only.
2016.10.28
  • Bit 16 updated Transmit Descriptor table
  • Updated "Clock Structure"
  • Added "Clock Structure"
2016.05.27 Removed references to the Application Interface (also known as the switch interface). This feature is not supported in this device.
2016.05.03 Maintenance release.
2015.11.02
  • Added emac_phy_mac_speed_o signals to "FPGA EMAC I/O Signals" section
  • Added the following subsections in the "Layer 3 and Layer 4 Filters" section:
    • Layer 3 and Layer 4 Filters Register Set
    • Layer 3 Filtering
    • Layer 4 Filtering
  • Added internal clock diagram to "Clock Structure" section
2015.05.04
  • Corrected IEEE 1588 timestamp resolution in the "EMAC Block Diagram and System Integration" section and the "IEEE 1588-2002 Timestamps" section
  • Added clarification for phy_txclk_o and phy_clk_rx_i in the "HPS EMAC I/O Signals"
  • Added subsections "Ordinary Clock," "Boundary Clock," "End-to-End Transparent Clock" and "Peer-to-Peer Transparent Clock" in the "Clock Type" section
  • Added clarification in the "EMAC Module Clock Inputs and Outputs" table for the description of phy_clk_rx_i in the "Clock Structure" section
  • Added "EMAC ECC RAM Reset" subsection in "Taking the Ethernet Out of Reset" section
  • Added address map and register definitions
2014.12.06
  • Added Application Interface sub-section to Features Section.
  • Updated EMAC Block Diagram and System Integration section with new diagram and information.
  • Added Signal Descriptions section.
  • Added EMAC Internal Interfaces section.
  • Added TX FIFO and RX FIFO subsection to the Transmit and Receive Data FIFO Buffers section.
  • Updated Descriptor Overview section to clarify support for only enhanced (alternate) descriptors.
  • Added Destination and Source Address Filtering Summary in Frame Filtering Section.
  • Added Clock Structure sub-section to Clocks and Resets section
  • Added Application Interface to FPGA Fabric section in Functional Description of EMAC
  • Added System Level EMAC Configuration Registers section in Ethernet Programming Model
  • Added EMAC Interface Initialization for FPGA GMII/MII Mode section in Ethernet Programming Model
  • Added EMAC Interface Initialization for RGMII/RMII Mode section in Ethernet Programming Model
  • Corrected DMA Initialization and EMAC Initialization and Configuration titles to appear on correct initialization information
  • Removed duplicate programming information for DMA
  • Added Taking the Ethernet MAC Out of Reset section.
2014.08.18 Initial release.
Ethernet Media Access Controller

Document Version

Changes

2018.01.26 Added steps for enabling ECC.
2016.10.28 Maintenance release.
2016.05.03 Maintenance release.
2015.11.02
  • Renamed "ULPI PHY Interface" section to "USB 2.0 ULPI PHY Signal Description" and moved it after the "USB OTG Controller Block Diagram and System Integration" section.
  • Removed references to LPM mode in document, including "LPM Function" section
  • Added "DMA" section
  • Added "Clock Gating" section
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the USB OTG Out of Reset section.

2014.08.18

Initial release.

USB 2.0 OTG Controller
Document Version Changes
2015.11.02
  • Renamed "Interface Pins" section to "Interface to HPS I/O" and moved it under the "SPI Controller Signal Description" section
  • Moved "FPGA Routing" section under "SPI Controller Signal Description" Section
  • Added Clock Gating information
  • Added Multi-Master mode to "Features of the SPI Controller" section
  • Updated "RXD Sample Delay" section
  • Updated "Glue Logic for Master Port ss_in_n" section
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the SPI Out of Reset section.
2014.08.18 Initial release.
SPI Controller
Document Version Changes
2015.11.02
  • Renamed Interface Pins section to I2C Controller Signal Description and moved section below I2C Controller Block Diagram and System Integration
2015.05.04
  • Added Impact of SCL Rise Time and Fall Time On Generated SCL figure to Clock Synchronization section
  • Updated Minimum High and Low Counts section
2014.12.15
  • Maintenance release.
  • Added Taking the I2C Out of Reset section.
2014.08.18 Initial release.
I2C Controller
Document Version Changes
2015.11.02 Renamed Interface Pins section to HPS I/O Pins and moved this section and FPGA Routing under UART Controller Signal Description
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the UART Out of Reset section.
2014.08.18 Initial release.
UART Controller
Document Version Changes
2014.12.15
  • Maintenance release.
  • Added Taking the GPIO Out of Reset section.
2014.08.18 Initial release.
General-Purpose I/O Interface
Version Changes
2014.08.18 Initial release.
Timer
Document Version Changes
2015.11.02 Added note to "Watchdog Timer Counter" section.
2015.05.04 Maintenance release.
2014.12.15
  • Maintenance release.
  • Added Taking the Watchdog Timer Out of Reset section.
2014.08.18 Initial release
Watchdog Timer
Table 5.  Hard Processor System I/O Pin Multiplexing Revision History

Document Version

Changes

2019.06.14 Updated the PU_DRV_STRG and PD_DRV_STRG fields in the pinmux_dedicated_io_1 through pinmux_dedicated_io_17 registers in the io48_pin_mux_dedicated_io_grp.
2018.09.24 Updated the following section:
  • Features of the HPS I/O Block
2016.10.28 Maintenance release
2016.05.27 Maintenance release.
2016.05.03 Maintenance release
2015.11.02 Maintenance release
2015.05.04 Added address maps and register definitions
2014.08.18 Initial release

Document Version

Changes

2016.05.03 Removed FPGA‑to‑HPS SDRAM interface
2015.11.02 Maintenance release
2015.05.04 Maintenance release
2014.12.15 Maintenance release
2014.08.18 Initial release
Introduction to the HPS Component

Document Version

Changes
2023.01.10 Corrected the Enable UART Interrupts interface name, from s2f_usb1_interrupt to h2f_usb1_interrupt.
2016.05.27 Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported.
2016.05.03

Maintenance release.

2015.11.02 Added content regarding peripheral pin placement in HPS shared and dedicated I/O to the "Configuring Peripherals" section.
2015.05.04
  • Updated "Reset Interfaces" section.
  • Updated "General Interfaces" section.

2014.12.15

Initial release.

Instantiating the HPS Component
Document Version Changes
2016.05.27 Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported.
2016.05.03 Maintenance release.
2015.11.02
  • Added "Platform Designer (Standard) Port Interface Mapping" section and subsections to "Peripheral Signal Interfaces"
2015.05.04 Maintenance release.
2014.12.15 Initial release.
HPS Component Interfaces
Table 6.  Simulating the HPS Component Revision History

Document Version

Changes

2016.05.27 Removed FPGA EMAC Switch Interface section. The application interface (also called the switch interface) is not supported.
2016.05.03 Removed references to FPGA to HPS SDRAM simulation.
2015.11.02 Added information about the signals on the "Advanced FPGA Placement" tab.
2015.05.04 Maintenance release.

2014.12.15

Maintenance release.

2014.08.15

Initial release.

Simulating the HPS Component
Document Version Changes
2018.11.02 Added note regarding SD card image partitioning in the SD/MMC Flash Devices section.
2017.12.15 Removed CM_PLL_CLK* signals from "Boot Source MUX Selects" table in Boot Source I/O Pins section
2017.07.22
  • Removed references to EOSC1 and replaced them with the correct external oscillator pin name, HPS_CLK1.
  • Clarified that the osc1_clk signal is sourced from the HPS_CLK1 pin.
2017.07.10
  • Modified note in the Booting and Configuration Options and Boot Select sections to remove statement requiring HPS to hold in reset until after the FPGA has been fully programmed.
  • Added a note regarding the necessity to prevent the HPS from being held in cold or warm reset indefinitely in the Reset, FPGA Configuration and Full FPGA Reconfiguration sections.
2017.05.31
  • Added note regarding SmartVID and early I/O release to the sections FPGA Configuration and Early I/O Release FPGA Configuration Flow Through HPS.
  • Added I/O State section.
2016.10.28 Modified the "Remapping the On-Chip RAM" diagram in the "Typical Boot Flow (Non-secure)" section
2016.05.27
  • Added Handling an FPGA Configuration Failure after Early I/O Release section.
  • Updated "Second-stage Boot Loader Image Layout" figure in the Loading the Second-Stage Boot Loader Image section.
  • Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.
2016.05.03
  • Updated SD/MMC device clock values in the CSEL Settings for SD/MMC Controller section.
  • Updated configuration sequence steps in the Arria 10 SoC FPGA Configuration Sequence Through FPGA Manager section.
  • Updated the reconfiguration sequence steps in the Arria 10 SoC FPGA Partial Reconfiguration Sequence Through FPGA Manager section.
  • Added bus mode to the "SD/MMC Controller Default Settings" table in the Default Settings of the SD/MMC Controller section.
2015.12.11 Updated the Full FPGA Reconfiguration section with the supported reconfiguration options.
2015.11.02 Added Intel® Quartus® Prime setting information to "Early I/O Release FPGA Configuration Through HPS" section
2015.06.12
  • Updated "Typical Second-Stage Loader Flow (Non-Secure)" figure in "Typical Boot Flow (Non-Secure)" section
  • Added content to "FPGA Overview"
  • Described I/O types and added details to booting option figures in "Booting and Configuration Options"
  • Added table to "Boot Fuses" section
  • Updated the CSEL setting tables in the "CSEL Settings for NAND Controller" section
  • Updated the "Quad SPI Controller Default Settings" table in the "Quad SPI Controller Default Settings" section
  • Updated the CSEL setting tables in the "Quad SPI Controller CSEL settings" section
  • Updated "Low-Level Boot Flow" figure in the "Typical Boot Flow (Non-Secure)" section
  • Added content regarding configuration flows in "FPGA Configuration" section
  • Added "Full FPGA Configuration Flow Through HPS" section
  • Added "Early I/O Release FPGA Configuration Flow Through HPS" section
  • Added "FPGA Reconfiguration" section with "Full FPGA Reconfiguration Section"
2015.05.04
  • Added more detail in the "FPGA Configures First" table of the "Booting and Configuration Options" section.
  • Added alternate "Boot Source Mux Selects" table in "Boot Source I/O Pins" section and "I/O Configuration" section.
  • Added more detail regarding booting from FPGA in the "Boot Select" section.
  • Added note in the "Boot ROM Flow" section about caches being enabled by the Boot ROM.
2014.12.15
  • Removed "Boot Stages" section.
  • The following sections were added:
    • "Boot ROM Flow"
    • "Typical Second-Stage Boot Flow"
    • "HPS State on Entry to the Preloader"
    • "Loading the Second-Stage Boot Image"
    • "FPGA Configuration" section with " Intel® Arria® 10 SoC FPGA Full Configuration" and " Intel® Arria® 10 SoC FPGA Partial Reconfiguration"
  • In the "Boot Definitions" section, "Boot Source I/O Pins", "Boot Fuses", and "Flash Memory Device" subsections were added.
2014.08.18

Initial release

Booting and Configuration