Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

2.2.3.2. Other HPS Interfaces

  • TPIU trace—sends trace data created in the HPS to the FPGA fabric
  • FPGA System Trace Macrocell (STM)—an interface that allows the FPGA fabric to send hardware events to be stored in the HPS trace data
  • FPGA cross–trigger—an interface that allows the CoreSight* trigger system to send triggers to IP cores in the FPGA, and vise versa
  • DMA peripheral interface—multiple peripheral–request channels
  • FPGA manager interface—signals that communicate with the FPGA fabric for boot and configuration
  • Interrupts—allow soft IP cores to supply interrupts directly to the MPU interrupt controller
  • MPU standby and events—signals that notify the FPGA fabric that the MPU is in standby mode and signals that wake up Cortex*-A9 processors from a wait for event (WFE) state
  • HPS debug interface – an interface that allows the HPS debug control domain (debug APB* ) to extend into FPGA

Another HPS–FPGA communications channel is FPGA clocks and resets.