Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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18.3.1. HPS EMAC I/O Signals

There are three EMACs available in the HPS. The following table lists the EMAC signals that can be routed from the EMACs to the HPS I/O pins. These signals provide the RMII/RGMII interface. For more information on routing EMAC signals to the FPGA and the HPS I/O, refer to the HPS Component Interfaces chapter.

Note: The "n" in EMACn stands for the EMAC peripheral number.
Table 177.  HPS EMAC I/O Signals

EMAC HPS I/O

In/Out

Width

Description

EMAC0_TX_CLK EMAC1_TX_CLK EMAC2_TX_CLK

Transmit Clock routed from one of three Platform Designer (Standard) port signals emac[2:0]_phy_txclk_o

Out

1

This signal provides the transmit clock for RGMII (125/25/2.5 MHz in 1G/100M/10Mbps).

This signal is one option for the common transmit and receive clock in RMII mode (50 MHz in 100M or 10 Mbps mode). The other possible source for the common transmit and receive clock is an external clock source, in which case EMACn_TX_CLK is left unconnected. In RMII mode, if this signal is the clock source for the receiver, then connect EMACn_TX_CLK to EMACn_RX_CLK.

All PHY transmit signals generated by the EMAC are synchronous to this clock.

EMAC0_TXD[3:0] EMAC1_TXD[3:0] EMAC2_TXD[3:0]

PHY Transmit Data, routed from one of three groups of Platform Designer (Standard) port signals emac[2:0]_phy_txd_o[3:0]

Out

4

This group of transmit data signals is driven by the MAC. Bits [3:0] provide the RGMII transmit data, and bits [1:0] provide the RMII transmit data. In RGMII mode, the data bus carries transmit data at double rate and are sampled on both the rising and falling edges of the transmit clock. The validity of the data is qualified with EMACn_TX_CTL.

EMAC0_TX_CTL EMAC1_TX_CTL EMAC2_TX_CTL

PHY Transmit Data Enable, routed from one of three Platform Designer (Standard) port signals emac[2:0]_phy_txen

Out

1

This signal is driven by the EMAC component. In RGMII mode, this signal acts as the control signal for the transmit data, and is driven on both edges of the transmit clock, EMACn_TX_CLK.

In RMII mode, this signal is high to indicate valid data.

EMAC0_RX_CLK EMAC1_RX_CLK EMAC2_RX_CLK

Receive Clock, routed to one of three Platform Designer (Standard) port signals emac[2:0]_clk_rx_i

In

1

In RGMII mode, this clock frequency is 125/25/2.5 MHz in 1 G/100 M/10 Mbps modes. It is provided by the external PHY. All PHY signals received by the EMAC are synchronous to this clock.

In RMII mode, this clock frequency is 50 MHz. The source of this clock can be:
  • An external source: In this case EMACn_TX_CLK should be left unconnected.
  • EMACn_TX_CLK: In this case, EMACn_TX_CLK must be connected to EMACn_RX_CLK.
EMAC0_RXD[3:0] EMAC1_RXD[3:0] EMAC2_RXD[3:0]

PHY Receive Data, routed to one of three groups of Platform Designer (Standard) port signals emac[2:0]_phy_rxd[3:0]

In

4

These data signals are received from the PHY. In RGMII mode, data is received at double data rate with bits[3:0] valid on the rising and falling edges of EMACn_RX_CLK. In RMII mode, data is received at single data rate with bits [1:0] valid on the rising edge of EMACn_RX_CLK. The validity of the data is qualified with EMACn_RX_CTL.

EMAC0_RX_CTL EMAC1_RX_CTL EMAC2_RX_CTL

PHY Receive Data Valid, routed to one of three groups of Platform Designer (Standard) port signals emac[2:0]_phy_rxdv.

In

1

This signal is driven by the PHY and functions as the receive control signal used to qualify the data received on EMACn_RXD[3:0]. This signal is sampled on both edges of the clock in RGMII mode.

See row above for clock to data relationships across the modes.