Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

2. Introduction to the Hard Processor System

The Intel® Arria® 10 system-on-a-chip (SoC) is composed of two distinct portions- a dual-core Arm* Cortex*-A9 hard processor system (HPS) and an FPGA. The HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system. A dedicated security manager within the HPS supports secure boot with the ability to authenticate, decrypt and provide tamper event response.

Figure 1 shows a high-level block diagram of the Intel® Arria® 10 SoC device. Blocks connected to device pins have symbols (square with an X) adjacent to them in the figure.

The SoC features the following types of I/O pins:

  • Dedicated I/O - I/O that is dedicated to an external non-volatile storage device (for boot ROM), HPS clock and resets.
  • Shared I/O - I/O that can be assigned to peripherals in the HPS or FPGA logic.
  • FPGA I/O - I/O that is dedicated to the FPGA fabric.
Figure 1.  Intel® SoC Device Block Diagram

The HPS consists of the following types of modules:

  • Microprocessor unit (MPU) subsystem with a dual Arm* Cortex*-A9 MPCore* processors
  • Flash memory controllers
  • SDRAM L3 interconnect
  • System interconnect
  • On-chip memories
  • Support peripherals
  • Interface peripherals
  • Debug components
  • Phase-locked loops (PLLs)

The HPS incorporates third-party intellectual property (IP) from several vendors.

The dual-processor HPS supports symmetric (SMP) and asymmetric (AMP) multiprocessing.

The FPGA portion of the device contains:

  • FPGA fabric
  • Configuration sub-system (CSS)
  • PLLs
  • High-speed serial interface (HSSI) transceivers, depending on the device variant
  • Hard PCI Express* (PCI-e) controllers
  • Hard memory controllers

The HPS and FPGA communicate with each other through bus interfaces that bridge the two distinct portions. On a power-on reset, the HPS can boot from multiple sources, including the FPGA fabric and external flash. The FPGA can be configured through the HPS or an externally supported device.

The HPS and FPGA portions of the device each have their own pins. The HPS has dedicated I/O pins and can also share some FPGA I/O pins. Pin assignments are configured when the HPS component is instantiated in Platform Designer (Standard). At boot time, software executing on the HPS assigns the I/O pins to the available HPS modules and configures the I/O pins through I/O control registers. For more information, refer to the "Hard Processor System I/O Pin Multiplexing" chapter. The FPGA I/O pins are configured by an FPGA configuration image through the HPS or any external source supported by the device.

The FPGA fabric and the HPS must be powered at the same time. Once powered, the FPGA fabric and the HPS can be configured independently thus providing you with more design flexibility:

  • You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller.
  • You can configure the FPGA fabric first, and then boot the HPS from the memory accessible to the FPGA fabric.