Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

16.5.4. Indirect Write Operation with DMA Disabled

The following steps describe the general software flow to set up the quad SPI controller for indirect write operation with the DMA disabled:

  1. Perform the steps described in the Setting Up the Quad SPI Flash Controller section.
  2. Set the flash memory start address in the indwrstaddr register.
  3. Set up the number of bytes to be transferred in the indwrcnt register.
  4. Set the indirect transfer trigger address in the indaddrtrig register.
  5. Set up the required interrupts through the interrupt mask register (irqmask).
  6. Start the indirect write operation by setting the start field of the indwr register to 1.
  7. Either use the watermark level interrupt or poll the SRAM fill level in the sramfill register to determine when there is sufficient space in the SRAM.
  8. Issue a write transaction to the indirect address to write one flash page of data to the SRAM. Repeat 8 if more write transactions are needed to complete the indirect write transfer. The final write may be less than one page of data.