Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

26.3.4.3. Shared Pin MUX Registers

There are 48 shared pin MUX registers, one for each shared I/O pin. The pin MUX register names correspond to the signal names, as listed in the following table.

Table 226.  Shared Pin MUX Register Names and Signals
Shared Pin MUX Register Name HPS Signal Name FPGA Signal Name
pinmux_shared_io_q1_1 HPS_SHARED_IO_Q1_1 FPGA_SHARED_IO_Q1_1
... ... ...
pinmux_shared_io_q1_12 HPS_SHARED_IO_Q1_12 FPGA_SHARED_IO_Q1_12
pinmux_shared_io_q2_1 HPS_SHARED_IO_Q2_1 FPGA_SHARED_IO_Q2_1
... ... ...
pinmux_shared_io_q2_12 HPS_SHARED_IO_Q2_12 FPGA_SHARED_IO_Q2_12
pinmux_shared_io_q3_1 HPS_SHARED_IO_Q3_1 FPGA_SHARED_IO_Q3_1
... ... ...
pinmux_shared_io_q3_12 HPS_SHARED_IO_Q3_12 FPGA_SHARED_IO_Q3_12
pinmux_shared_io_q4_1 HPS_SHARED_IO_Q4_1 FPGA_SHARED_IO_Q4_1
... ... ...
pinmux_shared_io_q4_12 HPS_SHARED_IO_Q4_12 FPGA_SHARED_IO_Q4_12

Each shared pin MUX register contains a 4-bit MUX select field to select the function of the shared I/O pin. At a cold reset event these fields default to 15, selecting a general purpose I/O function. A warm reset event does not affect these registers.

Note: Although the shared I/O pins are configured through the control registers, software cannot reconfigure the shared I/O pins after I/O configuration is complete. There is no support for dynamically changing the pin MUX selections for shared pins.