Intel® Arria® 10 Hard Processor System Technical Reference Manual
A newer version of this document is available. Customers should click here to go to the newest version.
29.1.1. FPGA-to-HPS Bridge
Interface Name |
Description |
Associated Clock Interface |
---|---|---|
|
FPGA-to-HPS AXI slave interface |
|
The FPGA-to-HPS interface is a configurable data width AXI slave allowing FPGA masters to issue transactions to the HPS. This interface allows the FPGA fabric to access the majority of the HPS slaves. This interface also provides a coherent memory interface.
Other interface standards in the FPGA fabric, such as connecting to Avalon® Memory-Mapped (Avalon-MM) interfaces, can be supported through the use of soft logic adapters. The Platform Designer (Standard) system integration tool automatically generates adapter logic to connect AXI to Avalon-MM interfaces.
The FPGA-to-HPS interface is an AXI-3 compliant interface with the following features:
- Configurable data width: 32, 64, or 128 bits
- Ready latency support data widths: 32, 64, or 128 bits