Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

30.15. Pin MUX and Peripherals

Under Pin MUX and Peripherals, the Pin Mux GUI has three folder tabs with the following functions:
  • IP Selection
  • Advanced Pin Placement
  • Advanced FPGA Placement
The IP Selection tab contains two sub-windows. In the left sub-window, you are able to select the following:
  • Boot source — SD/MMC, NAND, and QSPI
  • Pin routing decisions between:
    • IP and HPS I/O—where your selections are reflected on the Advanced Pin Placement
    • IP and FPGA—where your selections are reflected on the Advanced FPGA Placement
  • NAND bit-width when the NAND IP is selected
  • SD/MMC bit-width and SD/MMC Power Enable when the SD/MMC IP is selected
  • RGMII and PHY Options for each of the EMACs when the EMAC IP is selected
  • Additional QSPI Slave Selects when the QSPI IP is selected

After you have made your selection, you must click on the Apply Selections button and select "Show signals" so that you can see your selection reflected in the right sub-window. Depending on if you are routing to the HPS I/O or the FPGA, your selection is reflected on the Advanced Pin Placement or Advanced FPGA Placement tab, respectively.