Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.6. Resets

Power-On-Reset (POR) Reset

The security manager handles clocking during POR. Depending on the status of one of the security fuses, the device is initially clocked using either the secure cb_intosc_hs_div2_clk or the unsecure external oscillator.

Cold Reset

The reset manager brings the clock manager out of cold reset first in order to provide clocks to the rest of the blocks. After POR is de-asserted, clock manager enables boot_clk to the rest of the system before the module resets are de-asserted.

Warm Reset

During a Warm Rest, the clock manager module is not reset. The following steps are taken during a warm reset:

  1. Reset manager puts all modules affected by Warm Reset into reset. Reset manager issues a Boot Mode request to clock manager.
  2. Based on the status of the hps_clk_f fuse during POR, security manager indicates if the boot clock should be secure.
    1. If secure clocks are enabled, boot_clk transitions gracefully to cb_intosc_hs_div2_clk.
    2. If secure clocks are not enabled, boot_clk transitions gracefully to the external oscillator input, HPS_CLK1.
    Note: The security fuse is only sampled during cold reset and warm reset. The security fuse hps_clk_f allows the user to enable secure clocks. If clearing RAM on a Cold or Warm reset, the user should enable secure clocks (cb_intosc_hs_clk divide by 2).
  3. The Clock Manager gracefully transitions Hardware-Managed and Software Managed clocks into Boot Mode as follows:
    1. Disable all output clocks including Hardware and Software-Managed clocks.
    2. Wait for all clocks to be disabled, and do the following two things:
      1. Bypass all external Hardware and Software-Managed clocks.
      2. Update Hardware-Managed external counters/dividers to Boot Mode settings.
    3. Wait for all bypasses to switch, and then synchronously reset the CSR registers.
    4. Enable all clocks.
  4. After Hardware Managed Clocks have transitioned, the Clock Manager acknowledges the Reset Manager.
  5. Reset Manager continues with Warm Reset de-assertion sequence.