Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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Document Table of Contents

2.1. Features of the HPS

The main modules of the HPS are:

  • MPU subsystem featuring a dual-core Arm* Cortex*-A9 MPCore* processor
  • System interconnect that includes three memory-mapped interfaces between the HPS and FPGA:
    • HPS-to-FPGA: 32-, 64-, or 128-bit wide AXI-4
    • Lightweight HPS-to-FPGA: 32-bit wide AXI-4
    • FPGA-to-HPS: 32-, 64-, or 128-bit wide ACE
  • General-purpose direct memory access (DMA) controller
  • Security manager
  • Supports peripheral memories with single-error correction and double-error detection (SECDED)
  • Three Ethernet media access controllers (EMACs)
  • Two USB 2.0 on-the-go (OTG) controllers
  • NAND flash controller
  • Quad serial peripheral interface (QSPI) flash controller
  • Secure digital/multimedia card (SD/MMC) controller
  • Two serial peripheral interface (SPI) master controllers
  • Two SPI slave controllers
  • Five inter-integrated circuit (I2C) controllers1
  • 256 KB on-chip RAM
  • 128 KB on-chip boot ROM
  • Two UARTs
  • Four system timers
  • Two watchdog timers
  • Three general-purpose I/O (GPIO) interfaces
  • Arm* CoreSight* debug components:
    • Debug access port (DAP)
    • Trace port interface unit (TPIU)
    • System trace macrocell (STM)
    • Program trace macrocell (PTM)
    • Embedded trace router (ETR)
    • Embedded cross trigger (ECT)
  • System manager
  • Clock manager
  • Reset manager
  • FPGA manager
1 Three of the five I2Cs, can optionally be configured to provide PHY management support for each EMAC controller.