Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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28.3.2.1. User Clock Parameters

The frequencies that you provide are the maximum expected frequencies. The actual clock frequencies can be modified through the register interface, for example by software running on the microprocessor unit (MPU). For further details, refer to Selecting PLL Output Frequency and Phase.

Parameter Name

Parameter Description

Clock Interface Name

Enable HPS-to-FPGA user 0 clock

Enable main PLL from HPS-to-FPGA

h2f_user0_clock

User 0 clock frequency

Specify the maximum expected frequency for the main PLL

Enable HPS-to-FPGA user 1 clock

Enable peripheral PLL from HPS-to-FPGA

h2f_user1_clock

User 1 clock frequency

Specify the maximum expected frequency for the peripheral PLL