Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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9.3.1.2. FPGA-to-HPS Bridge Slave Signals

The FPGA-to-HPS bridge slave address channels support user-sideband signals, routed to the ACP in the MPU subsystem. All the signals have a fixed width except the data and write strobes for the read and write data channels. The variable width signals depend on the data width setting of the bridge.

The FPGA-to-HPS bridge incorporates Arm* 's TrustZone* technology by providing the ARPROT[1] and AWPROT[1] signals, which specify whether a transaction is secure or nonsecure. The firewall logic uses the AxPROT signals to determine if a bus transaction matches the security level allowed. You can program security values in the Secure Configuration Registers of the system interconnect.

All peripheral slaves and memories in the SoC are secure when they are released from reset.

The following tables list all the signals exposed by the FPGA-to-HPS slave interface to the FPGA fabric.

Table 69.  FPGA-to-HPS Bridge Slave Write Address Channel Signals
Signal Width Direction Description
AWID

8 bits

Input

Write address ID

AWADDR

32 bits

Input

Write address

AWLEN

4 bits

Input

Burst length

AWSIZE

3 bits

Input

Burst size

AWBURST

2 bits

Input

Burst type

AWLOCK

2 bits

Input

Lock type—Valid values are 00 (normal access) and 01 (exclusive access)

AWCACHE

4 bits

Input

Cache policy type

AWPROT

3 bits

Input

Protection type

AWVALID

1 bit

Input

Write address channel valid

AWREADY

1 bit

Output

Write address channel ready

AWUSER

5 bits

Input

User sideband signals

Table 70.  FPGA-to-HPS Bridge Slave Write Data Channel Signals
Signal Width Direction Description
WID

8 bits

Input

Write ID

WDATA

32, 64, or 128 bits

Input

Write data

WSTRB

4, 8, or 16 bits

Input

Write data strobes

WLAST

1 bit

Input

Write last data identifier

WVALID

1 bit

Input

Write data channel valid

WREADY

1 bit

Output

Write data channel ready

Table 71.  FPGA-to-HPS Bridge Slave Write Response Channel Signals
Signal Width Direction Description
BID

8 bits

Output

Write response ID

BRESP

2 bits

Output

Write response

BVALID

1 bit

Output

Write response channel valid

BREADY

1 bit

Input

Write response channel ready

Table 72.  FPGA-to-HPS Bridge Slave Read Address Channel Signals
Signal Width Direction Description
ARID

8 bits

Input

Read address ID

ARADDR

32 bits

Input

Read address

ARLEN

4 bits

Input

Burst length

ARSIZE

3 bits

Input

Burst size

ARBURST

2 bits

Input

Burst type

ARLOCK

2 bits

Input

Lock type—Valid values are 00 (normal access) and 01 (exclusive access)

ARCACHE

4 bits

Input

Cache policy type

ARPROT

3 bits

Input

Protection type

ARVALID

1 bit

Input

Read address channel valid

ARREADY

1 bit

Output

Read address channel ready

ARUSER

5 bits

Input

Read user sideband signals

Table 73.  FPGA-to-HPS Bridge Slave Read Data Channel Signals
Signal Width Direction Description
RID

8 bits

Output

Read ID

RDATA

32, 64, or 128 bits

Output

Read data

RRESP

2 bits

Output

Read response

RLAST

1 bit

Output

Read last data identifier

RVALID

1 bit

Output

Read data channel valid

RREADY

1 bit

Input

Read data channel ready