Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4.1. HPS Address Spaces

The following table shows the HPS address spaces and their sizes.

Table 7.  HPS Address Spaces

Name

Description

Size

MPU

MPU subsystem

4 GB

L3

System interconnect

4 GB

SDRAM

SDRAM region

4 GB

Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space has the peripheral, FPGA slaves, SDRAM window, and boot regions.

The following figure shows the relationships between the HPS address spaces. The figure is not to scale.

Figure 3. HPS Address Space Relationships

The SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue vertical arrows) at the expense of the FPGA slaves and boot regions. For specific details, refer to “MPU Address Space”.

The following table shows the base address and size of each region that is common to the L3 and MPU address spaces.
Table 8.  Common Address Space Regions

Region Name

Base Address

Size

FPGA slaves

0xC0000000

960 MB

Peripheral

0xFC000000

64 MB

Lightweight FPGA slaves

0xFF200000

2 MB