Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3.7. Clock

The FPGA manager has two clock input signals which are asynchronous to each other. The clock manager generates these two clocks:

  • cfg_clk—the configuration slave interface clock input and also the DCLK output reference for FPGA configuration. Enable this clock in the clock manager only when configuration is active or when the configuration slave interface needs to respond to master requests.
  • l4_mp_clk—the register slave interface clock.