Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

14.4.5. Clocks

The NAND clock runs synchronously from the NOC clocks, which is always active. To minimize the number of clocks, Clock Manager outputs software managed enables to the USB, SPI Masters, QSPI and NAND peripherals. The software enable for NAND is nand_clk_en and is set to ENABLE by default. Also, in Boot Mode, nand_clk_en is active to ensure that all clocks are active if RAM is cleared for security.

Table 121.  Clock Inputs to NAND Flash Controller
Clock Signal Description
nand_x_clk

Clock for master and slave interfaces and the ECC sector buffer.

nand_clk

Clock for the NAND flash controller.

The frequency of nand_x_clk is four times the frequency of nand_clk.