Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.2.9.1.1.1. Exclusive Access Support

To ensure mutually exclusive access to shared data, use the exclusive access support built into the SDRAM scheduler. The AXI buses that interface to the scheduler provide ARLOCK[0] and AWLOCK[0], signals which are used by the scheduler to arbitrate for exclusive access to a memory location. The SDRAM scheduler contains six monitors. Each monitor can be used by any of the following exclusive-capable masters:

  • CPU 0
  • CPU 1
  • FPGA-to-HPS bridge
  • FPGA-to-SDRAM0 port
  • FPGA-to-SDRAM1 port
  • FPGA-to-SDRAM2 port

Each master can lock only one memory location at a time.