Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.2. Functional Description of the System Interconnect

The system interconnect provides access to a 4 GB address space.

Address spaces are divided into one or more nonoverlapping contiguous regions.

Figure 35. HPS Address Space RelationshipsPositions of HPS address spaces. For readability, some memory regions are shown out-of-scale to their addresses.

The window regions provide access to other address spaces. The thin black arrows indicate which address space is accessed by a window region (arrows point to accessed address space).

The following table shows the base address and size of each region that is common to the L3 and MPU address spaces.

Table 44.  Common Address Space Regions
Region Name Description Base Address Size
FPGASLAVES FPGA slaves 0xC0000000 960 MB
PERIPH Peripheral 0xFC000000 64 MB
LWFPGASLAVES 8 Lightweight FPGA slaves 0xFF200000 2 MB
8 The LWFPGASLAVES region is part of the "PERIPH" region.