Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.2.7. Functional Description of the Rate Adapters

Rate adapters are used at points in the system interconnect where there are bandwidth discontinuities, to ensure efficient use of interconnect data pathways. They are placed where a low-bandwidth source feeds a high-bandwidth destination. For this reason, they are sometimes positioned at the response side (where the Master is faster) and sometimes at the request side (where the Slave is faster).

The following table shows the rate adapters.

Table 52.  Rate Adapter Modules
Rate Adapter Module Name Data Path
noc_mpu_m0_MPU_M1toDDRResp_main_RateAdapter Data packets from the SDRAM L3 interconnect in response to the MPU
noc_mpu_m0_MPU_M0_rate_adResp_main_RateAdapter Data packets from the L3 interconnect in response to the MPU
noc_mpu_m0_L4_MP_rate_ad_main_RateAdapter Data packets carrying requests from L4 master peripherals to the L3 interconnect
noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter Data packets carrying requests from the FPGA-to-HPS bridge master to the L3 interconnect
noc_mpu_m0_L3Tosoc2fpgaResp_main_RateAdapter Data packets from the HPS-to-FPGA and lightweight HPS-to-FPGA bridges in response to the L3 interconnect
noc_mpu_m0_acp_rate_ad_main_RateAdapter Data packets carrying requests from the L3 interconnect to the ACP