Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683063
Date 1/11/2022
Public
Document Table of Contents

3.3.2. Clocking Scheme

The following diagrams show the clocking scheme for the design example.

Figure 19. Clocking Scheme for Ethernet Design Example with IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.
Figure 20. Clocking Scheme for Ethernet Design Example without IEEE 1588v2 Feature
Note: The IOPLL input reference clock is sourcing from input clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network may introduce additional jitter to the ATX/FPLL/IOPLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.