Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents Typical Use Cases

  • You can assert the reset_req signal from power-on to prevent the Nios® V processor core from starting program execution from its reset vector until other FPGA hosts in the system initialize the Nios® V processor boot memory. In this case, the entire subsystem can experience a clean hardware reset. The Nios® V processor is held indefinitely in a reset request state until the other FPGA hosts initialize the processor boot memory.
  • In a system where you must reset the Nios® V processor core without disrupting the rest of the system, you can assert the reset_req signal to cleanly halt the current operation of the core. Restart the processor from the reset vector once the system releases the reset_req_ack signal.
  • An external host can use the reset request interface to ease the implementations of the following tasks:
    • Halt the current Nios® V processor program.
    • Load a new program into the Nios® V processor boot memory.
    • Allow the processor to begin executing the new program.
Altera recommends you to implement a timeout mechanism to monitor the state of reset_req_ack signal. If Nios® V processor core falls into an infinite wait state condition and stall with an unknown reason, reset_req_ack cannot assert indefinitely. The timeout mechanism enables you to:
  • Define a recovery timeout period and perform system recovery with system level reset.
  • Perform a hardware level reset.