Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Public
Document Table of Contents

4.7.1.1. Hardware Design Flow

The following sections describe a step-by-step method for building a bootable system for a Nios® V processor application from TCM. The example below is built using Arria® 10 SoC development kit.

IP Component Settings

  1. Create your Nios® V processor project using Quartus® Prime and Platform Designer.
    Figure 80. Connections for Nios® V Processor Project
Note: Place all external peripheral IPs (e.g. JTAG UART, MSGDMA, PIO, and others) within a peripheral region. This requirement does not apply to dm_agent and timer_sw_agent.

TCM Settings for Nios® V Processor

  1. In the Nios® V processor parameter editor, enable the Instruction TCM1 and Data TCM1.
  2. Initialize Instruction TCM1 with itcm.hex.
  3. Initialize Data TCM1 with dtcm.hex.
    Figure 81. Instruction TCM1 Settings
    Figure 82. Data TCM1 Settings
  4. Align the base address of instruction_tcs1 to be the same as Instruction ITCM1 (0x40000).
Figure 83. Instruction_tcs1 Aligned Base Address

Reset Agent Settings for Nios® V Processor

  1. In the Nios® V processor parameter editor, set the Reset Agent to Instruction TCM1.
    Figure 84. Reset Agent Settings for Nios® V Processor
  2. Click Generate HDL, the Generation dialog box appears.
  3. Specify output file generation options and then click Generate.

Quartus® Prime Settings

  1. In the Intel Quartus Prime software, click Assignment > Device > Device and Pin Options > Configuration.
  2. Set Configuration scheme according to your FPGA configuration scheme
  3. Click OK to exit the Device and Pin Options window.
  4. Click OK to exit the Device window.
  5. Click Start Compilation to compile your project.