Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

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6.1.1. Pilot System with Non-pipelined Nios V/m Processor

Altera recommends to use the non-pipelined Nios® V/m processor to allow full debugging capabilities. The architecture performance of a non-pipelined Nios® V/m processor is similar to the Nios® V/c processor, at the expense of bigger logic size.

Table 39.   Nios® V/c and Nios® V/m Processor Core
Feature Nios® V/c Processor Non-pipelined Nios® V/m Processor
Debug Module Supported
Processor CSR Supported
Interrupt and Exceptions Supported
Logic Size (ALM) 10 x1 x1.5
DMIPS/Mhz Performance10 x1 x1
CoreMark/MHz Performance10 x1 x1
Internal Timer Supported
You can utilize Nios® V/m processor to debug Nios® V/c processor:
  1. Start the processor system using non-pipelined Nios® V/m processor.
    1. Turn on Enable Debug
    2. Turn off Enable Pipelining in CPU
  2. Ensure there is no interrupt or exception in the Nios® V/m processor system. Do not connect to the Interrupt Receiver on the processor.
    Note: To implement a JTAG UART Intel® FPGA IP without interrupt, you can enable the small JTAG UART driver in the BSP Editor to apply polled operation. Ensure that the compile definition (ALTERA_AVALON_JTAG_UART_SMALL) is found in the toolchain.cmake.
    Figure 103.  Nios® V/m Processor System with No Interrupt
    Figure 104. Enable Small JTAG UART Driver in BSP Editor
  3. Develop the Nios® V processor software application in baremetal ( Intel® HAL).
  4. Program the design SOF file onto the Intel® FPGA device.
  5. Download the application ELF file into the Nios® V processor system.
  6. Perform design verification and debugging with the Nios® V/m processor core.
  7. Verify that the Nios® V/m processor is working successfully, then replace the Nios® V/m processor with Nios® V/c processor.
    1. Right-click the Nios® V/m processor, click Replace > Nios V/c Processor Intel FPGA IP.
    2. Reconfigure the same assignment in the IP Parameter Editor.
    3. Address any possible errors.
    4. Click Sync System Infos.
    Figure 105.  Nios® V/c Processor Replacement
  8. Implement booting Nios® V/c processor from On-Chip Memory.
  9. Recreate the application BSP, APP, and ELF.
  10. Program the memory-initialized design SOF file onto the Intel® FPGA device.
  11. Power cycle the Intel® FPGA device.
10 Relative to the Nios® V/c processor.