Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

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4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM

In this method, the Nios® V processor reset address is set to the base address of the on-chip memory (OCRAM). The application binary (.hex) file is loaded into the OCRAM when the FPGA is configured, after the hardware design is compiled in the Quartus® Prime software. Once the Nios® V processor resets, the application begins executing and branches to the entry point.
  • Execute-In-Place from OCRAM does not require boot copier because Nios® V processor application is already in place at system reset.
  • Altera recommends enabling alt_load() for this booting method so that the embedded software behaves identically when reset without reconfiguring the FPGA device image.
  • You must enable the alt_load() function in the BSP Settings to copy the .rwdata section upon system reset. In this method, the initial values for initialized variables are stored separately from the corresponding variables to avoid overwriting on program execution.