Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents CPU Architecture

Table 14.  CPU Architecture Parameters
CPU Architecture Tab Description
Enable Floating Point Unit
  • Enable this option to add the floating-point unit (“F” extension) in the processor core.
mhartid CSR value
  • Hart ID register (mhartid) value is 0 at default.
  • Assign a value between 0 and 4094.
  • Compatible with Intel FPGA Avalon® Mutex Core HAL API.