Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Software Design Flow

This section provides the design flow to generate and build the Nios V processor software project. To ensure a streamlined build flow, you are encouraged to create similar directory tree in your design project. The following software design flow is based on this directory tree.

To create the software project directory tree, follow these steps:

1. In your design project folder, create a folder called software.

2. In the software folder, create two folders called app and bsp.

Figure 85. Software Project Directory Tree

Creating the Application BSP Project

To launch the BSP Editor, follow these steps:

  1. In the Platform Designer window, select File > New BSP. The Create New BSP windows appears.
  2. For BSP setting file, navigate to the software/bsp folder and name the BSP as settings.bsp.

    BSP path: <project directory>/software/bsp/settings.bsp

  3. For System file (qsys or sopcinfo), select the Nios® V/g processor Platform Designer system (.qsys) file.
    Note: For Quartus® Prime Standard Edition software, generate the BSP files using SOPCINFO. Refer to AN 980: Nios® V Processor Quartus® Prime Software Support for more information.
  4. For Quartus project, select the Quartus® Prime Project File.
  5. For Revision, select the correct revision.
  6. For CPU name, select the Nios® V/g processor.
  7. Select the Operating system as Altera HAL.
  8. Click Create to create the BSP file.
    Figure 86. Create New BSP Window

Configuring the BSP Editor and Generating the BSP Project

  1. Go to Main > Settings > Advanced > hal.linker.
  2. Enable allow_code_at_reset only.
    Figure 87. hal.linker Settings
  3. Click the BSP Linker Script tab in the BSP Editor
  4. In the Linker Section Name perform the following settings:
    1. Set .text and .exceptions to Instruction TCM1.
    2. Set the remaining Linker Section Name to the Data TCM1.
      Figure 88. Linker Region Settings for TCM
  5. Click Generate BSP. Make sure the BSP generation is successful.
  6. Close the BSP Editor

Generating the Application Project File

  1. Navigate to the software/app folder and create your user application source code.
  2. Launch the Nios V Command Shell.
  3. Execute the command below to generate the user application CMakeLists.txt.
niosv-app --app-dir=software/app --bsp-dir=software/bsp \
    --srcs=software/app/<user application>

Building the Application Project

You can choose to build the application project using RiscFree* IDE for Intel FPGAs, Eclipse Embedded CDT, or through the command line interface (CLI).

If you prefer using CLI, you can build the application using the following command:

cmake -G "Unix Makefiles" -B software/app/build -S software/app
make -C software/app/build
The user application (.elf) file is created in software/app/build folder.

Generating the HEX File

You must generate a .hex file from your application .elf file, so you can create a .jic file suitable for programming flash devices.

  1. Launch the Nios V Command Shell.
  2. For Nios® V processor application boot from TCM, use the following command line to convert the ELF to HEX for your application. This command creates the user application (itcm.hex and dtcm.hex) file.
    elf2hex software/app/build/<user_application>.elf -o itcm.hex \
        -b <base address of ITCM> -w 32  \
        -e <end address of ITCM> -r 4
    elf2hex software/app/build/<user_application>.elf -o dtcm.hex \
        -b <base address of DTCM> -w 32 \
        -e <end address of DTCM> -r 4
  3. Recompile the hardware design to memory-initialize both the HEX files into the Instruction TCM and Data TCM.