Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

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2.7. JTAG Signals

The Nios® V processor debug module uses the JTAG interface for software ELF download and software debugging. When you debug your design with the JTAG interface, the JTAG signals TCK, TMS, TDI, and TDO are implemented as part of the design. Specifying the JTAG signal constraints in every Nios V processor system is an important system design consideration and is required for correctness and deterministic behavior.