Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer

To generate simulation files, perform the following steps:

  1. Start the Intel Quartus Prime software and open the Platform Designer from the Tools menu.
  2. Open the <your project design>.qsys file.
    Note: Ensure that you have completed building your Platform Designer system before generating the simulation models
  3. In Platform Designer, navigate to Generate > Generate Testbench System.
  4. On the Generation window, set the following parameters to these values:
    1. Create testbench Platform Designer system— Standard, BFMs for standard Platform Designer interfaces.

      Note: If your system has exported ports other than the clock and reset, choose Standard, BFMs for standard Avalon interfaces.

    2. Create testbench simulation model—Verilog
    3. Select Use multiple processors for faster IP generation (when available).
  5. Click Generate, and Save, if prompted.
Figure 107. Testbench Generation